From patchwork Tue Apr 4 13:05:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 670490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8638C761A6 for ; Tue, 4 Apr 2023 13:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234855AbjDDNI6 (ORCPT ); Tue, 4 Apr 2023 09:08:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233979AbjDDNI5 (ORCPT ); Tue, 4 Apr 2023 09:08:57 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8071C198A for ; Tue, 4 Apr 2023 06:08:55 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id e9so18487339ljq.4 for ; Tue, 04 Apr 2023 06:08:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680613734; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s1S4RadLv40VaSLEeL6kAMgf+t+s7tSqqlEujsdEUl4=; b=HrzvsGJPSqgK0OWk7Sfm2KCJYWycJHfZd83WtLIimuFNChEurI6/Krl0KH6pUqKtwT F3CrLINMjJjNIfMTkmqGFm+vG6MibxPZsJWvF6TONZben/fHeG3yk5eu+fTzPCOW1jYM Jwm5QG86fVudEC8qP1rxzVfGNdOZBVZpxNP2+jg/d0s5UYWpEFzNMl/R2azOt5NWTEMl L0xXjLWAE5NuWpGXJt+rPwjyJJfg2DkfiqeMsLcTw0UAka9GLVGuOKdGnnecU9X7zKuU a+Hfc8yQSUUbAH2tA4zQf0Nc7fQYo7qTFTkcQQIk1nE44VYuYSmNWVoqzdJ2QOSJ/efj I92g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680613734; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s1S4RadLv40VaSLEeL6kAMgf+t+s7tSqqlEujsdEUl4=; b=fuDgoYvy1fNcJeVvWqdzSYYRPsMErdbHAvd25uPTihC5QoGZ+hq6usJ378hLtoxGpG Pepb4ghOheRdqiJZCmulm9aTrDpJG0Xu/153zo6HYdb0KmHkFZKfMSqlCijGuRKkYnF4 4Sy+LYcPix0UhTFw3LIcc90RyyOcOCXC+xbhn23epyOpwwFLtcT2yE17ydfHsuixLrf9 sQu1UNdP+ZgTgtnrE7xD+mAbGIgZ4a53UbJksK1f3Y7XJnOpFLY9tFqw7z/0iVSEayJe tMLxobPp6AvCtORI6kl3wXTTFVUsZTC1rXC74jfuEHocmDaGQR89iPQkUVUsAHmH9Q4n 4Siw== X-Gm-Message-State: AAQBX9c3ThPgtdYavHjBORnyAiAeFc9lqj3ynkWS1l3STGdt44jFtn1r B8uc41txti14jB2QnVQE/vNFmQ== X-Google-Smtp-Source: AKy350ZN+3MHnEk366WLvPECDlAXX8UESmMQrhj0NoT6sfYpFBcqqkk5uVkPgNTdZUJvhHPv4ip+wg== X-Received: by 2002:a2e:914b:0:b0:295:9906:64e4 with SMTP id q11-20020a2e914b000000b00295990664e4mr774374ljg.2.1680613733857; Tue, 04 Apr 2023 06:08:53 -0700 (PDT) Received: from eriador.lumag.spb.ru ([193.65.47.217]) by smtp.gmail.com with ESMTPSA id c11-20020a05651c014b00b0029e5448e752sm2304789ljd.131.2023.04.04.06.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Apr 2023 06:08:53 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio Subject: [PATCH v4 16/42] drm/msm/dpu: split SC8180X catalog entry to the separate file Date: Tue, 4 Apr 2023 16:05:56 +0300 Message-Id: <20230404130622.509628-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230404130622.509628-1-dmitry.baryshkov@linaro.org> References: <20230404130622.509628-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 107 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 105 +---------------- 2 files changed, 108 insertions(+), 104 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h new file mode 100644 index 000000000000..cd505605be1f --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_5_1_SC8180X_H +#define _DPU_5_1_SC8180X_H + +static const struct dpu_caps sc8180x_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED3, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 4096, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + +static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_30, + .highest_bank_bit = 0x3, +}; + +static const struct dpu_mdp_cfg sc8180x_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x45c, + .features = BIT(DPU_MDP_AUDIO_SELECT), + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + }, +}; + +static const struct dpu_intf_cfg sc8180x_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), + INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21), + INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23), +}; + +static const struct dpu_perf_cfg sc8180x_perf_data = { + .max_bw_low = 9600000, + .max_bw_high = 9600000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +static const struct dpu_mdss_cfg sc8180x_dpu_cfg = { + .caps = &sc8180x_dpu_caps, + .ubwc = &sc8180x_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sc8180x_mdp), + .mdp = sc8180x_mdp, + .ctl_count = ARRAY_SIZE(sm8150_ctl), + .ctl = sm8150_ctl, + .sspp_count = ARRAY_SIZE(sdm845_sspp), + .sspp = sdm845_sspp, + .mixer_count = ARRAY_SIZE(sm8150_lm), + .mixer = sm8150_lm, + .pingpong_count = ARRAY_SIZE(sm8150_pp), + .pingpong = sm8150_pp, + .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), + .merge_3d = sm8150_merge_3d, + .intf_count = ARRAY_SIZE(sc8180x_intf), + .intf = sc8180x_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8150_regdma, + .perf = &sc8180x_perf_data, + .mdss_irqs = IRQ_SC8180X_MASK, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 08741f84151f..3db6e2379b93 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -361,20 +361,6 @@ static const struct dpu_caps sm8150_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_caps sc8180x_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0xb, - .qseed_type = DPU_SSPP_SCALER_QSEED3, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = 4096, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, - .max_hdeci_exp = MAX_HORZ_DECIMATION, - .max_vdeci_exp = MAX_VERT_DECIMATION, -}; - static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = { .ubwc_version = DPU_HW_UBWC_VER_10, .highest_bank_bit = 0x2, @@ -390,11 +376,6 @@ static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = { .highest_bank_bit = 0x2, }; -static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_30, - .highest_bank_bit = 0x3, -}; - static const struct dpu_mdp_cfg msm8998_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -447,30 +428,6 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = { }, }; -static const struct dpu_mdp_cfg sc8180x_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x45C, - .features = BIT(DPU_MDP_AUDIO_SELECT), - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2AC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { - .reg_off = 0x2B4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { - .reg_off = 0x2BC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { - .reg_off = 0x2C4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x2BC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { - .reg_off = 0x2C4, .bit_off = 8}, - }, -}; - /************************************************************* * CTL sub blocks config *************************************************************/ @@ -1093,16 +1050,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = { INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), }; -static const struct dpu_intf_cfg sc8180x_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x6A800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x6B000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ - INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), - INTF_BLK("intf_4", INTF_4, 0x6C000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21), - INTF_BLK("intf_5", INTF_5, 0x6C800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23), -}; - /************************************************************* * Writeback blocks config *************************************************************/ @@ -1426,33 +1373,6 @@ static const struct dpu_perf_cfg sm8150_perf_data = { .bw_inefficiency_factor = 120, }; -static const struct dpu_perf_cfg sc8180x_perf_data = { - .max_bw_low = 9600000, - .max_bw_high = 9600000, - .min_core_ib = 2400000, - .min_llcc_ib = 800000, - .min_dram_ib = 800000, - .danger_lut_tbl = {0xf, 0xffff, 0x0}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc7180_qos_linear), - .entries = sc7180_qos_linear - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - /* TODO: macrotile-qseed is different from macrotile */ - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - /************************************************************* * Hardware catalog *************************************************************/ @@ -1535,30 +1455,7 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = { .mdss_irqs = IRQ_SDM845_MASK, }; -static const struct dpu_mdss_cfg sc8180x_dpu_cfg = { - .caps = &sc8180x_dpu_caps, - .ubwc = &sc8180x_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sc8180x_mdp), - .mdp = sc8180x_mdp, - .ctl_count = ARRAY_SIZE(sm8150_ctl), - .ctl = sm8150_ctl, - .sspp_count = ARRAY_SIZE(sdm845_sspp), - .sspp = sdm845_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .pingpong_count = ARRAY_SIZE(sm8150_pp), - .pingpong = sm8150_pp, - .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), - .merge_3d = sm8150_merge_3d, - .intf_count = ARRAY_SIZE(sc8180x_intf), - .intf = sc8180x_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sm8150_regdma, - .perf = &sc8180x_perf_data, - .mdss_irqs = IRQ_SC8180X_MASK, -}; +#include "catalog/dpu_5_1_sc8180x.h" #include "catalog/dpu_6_0_sm8250.h" #include "catalog/dpu_6_2_sc7180.h"