From patchwork Mon Apr 3 09:23:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 669848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75E67C761A6 for ; Mon, 3 Apr 2023 09:23:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231982AbjDCJXo (ORCPT ); Mon, 3 Apr 2023 05:23:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232005AbjDCJXe (ORCPT ); Mon, 3 Apr 2023 05:23:34 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB273AF1A for ; Mon, 3 Apr 2023 02:23:17 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id x17so37205240lfu.5 for ; Mon, 03 Apr 2023 02:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680513796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QqGgu4Dq8CbrtExkjIjb7tdsKLrwoIcjoGCMDEsQeDA=; b=bW0U4kX1+wxGt0M5zEhQTMz+guvyKTy8np4HyrO0BAv4lxkbhOojAjt+lkgBkU/9AP 2TtbNWzLllqO8wzEvLIaFCQOWsmpmMm98CWeqi2b/8y6HsqSSmrpWnC8gby6ztzllnSR ZDlHukscvitf73KGLwadkavHeB5rfMaI+Koov6oYwcj4mNpyHdXBR+p/8/TNrCQBbO49 hKIRRFhLaCLk1XQIBUEGTslbDwyoAKcAyoEEK5yjqTf8GimUu3Iu4+YBLqutAvlN/0KN z3S6vYp1Ir64Bq9zXDKtzr3C2FBAopr6rVj5bId+/R+XH1Kx/yq/RUmF5F8P3DFx2znt p7Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680513796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QqGgu4Dq8CbrtExkjIjb7tdsKLrwoIcjoGCMDEsQeDA=; b=CS5Cl0C/KWM3unGKNm0rwPhQllGuE16rOJkwGgRJchNBeXlXoKhPX6Gz3QRfN62e2l DBEkkDJZdJ+N4LBO+uPlpu+Mx/uZYFpEriBjPXFEaMkJNNuAarSB/+uu1kmptdx3yQty Wq0NjG794YWbbAOfwD2N7/3pzuqEya4ur6AFfxst7V2qFxkbFtYmQV0WE9Ixt1FNJCp8 EppZFwLNFWDjVkNmE80ZwWIW7WfAVjLaI+R8jm7KdGCbVpV4nH3sYspjMH5UwdivsoUo PKubk8tIS65t8kPs8rt0i2IcPdXeNsDHGPc8OCyQtxD+oiF/FIFDyote0An71NfGYqSh E4vA== X-Gm-Message-State: AAQBX9eCafpLF3e33Yl55m0GIoLdQGzNwTLexOgJ1t5FMvScYJtOEykl JGPYxKhll5449yWqVzBBAAZaSw== X-Google-Smtp-Source: AKy350byfenKN5sDkT1FmLED6H0Xkt2urGWWQVCR8SjF3917Cph/6Q0QLCfgBuYEYRwRr46JtleTcw== X-Received: by 2002:ac2:428c:0:b0:4e6:3e36:cb3f with SMTP id m12-20020ac2428c000000b004e63e36cb3fmr10173374lfh.18.1680513796032; Mon, 03 Apr 2023 02:23:16 -0700 (PDT) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w5-20020ac25985000000b004e844bb6939sm1680666lfn.2.2023.04.03.02.23.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 02:23:15 -0700 (PDT) From: Dmitry Baryshkov To: David Airlie , Daniel Vetter , Jani Nikula , Suraj Kandpal , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Jani Nikula Subject: [PATCH v4 02/12] drm/i915/dsc: move rc_buf_thresh values to common helper Date: Mon, 3 Apr 2023 12:23:03 +0300 Message-Id: <20230403092313.235320-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230403092313.235320-1-dmitry.baryshkov@linaro.org> References: <20230403092313.235320-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The rc_buf_thresh values are common to all DSC implementations. Move them to the common helper together with the code to propagage them to the drm_dsc_config. Reviewed-by: Jani Nikula Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/display/drm_dsc_helper.c | 35 +++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------- include/drm/display/drm_dsc_helper.h | 1 + 3 files changed, 37 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index c869c6e51e2b..be91abe2cfb2 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -270,6 +270,41 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, } EXPORT_SYMBOL(drm_dsc_pps_payload_pack); +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ +static const u16 drm_dsc_rc_buf_thresh[] = { + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, + 7744, 7872, 8000, 8064 +}; + +/** + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model + * in accordance with the DSC 1.2 specification. + * + * @vdsc_cfg: DSC Configuration data partially filled by driver + */ +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg) +{ + int i; + + BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) != + DSC_NUM_BUF_RANGES - 1); + BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) != + ARRAY_SIZE(vdsc_cfg->rc_buf_thresh)); + + for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++) + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6; + + /* + * For 6bpp, RC Buffer threshold 12 and 13 need a different value + * as per C Model + */ + if (vdsc_cfg->bits_per_pixel == 6 << 4) { + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6; + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6; + } +} +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh); + /** * drm_dsc_compute_rc_parameters() - Write rate control * parameters to the dsc configuration defined in diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 7003ae9f683a..2fd08375bbe3 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -37,12 +37,6 @@ enum COLUMN_INDEX_BPC { MAX_COLUMN_INDEX }; -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ -static const u16 rc_buf_thresh[] = { - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, - 7744, 7872, 8000, 8064 -}; - struct rc_parameters { u16 initial_xmit_delay; u8 first_line_bpg_offset; @@ -543,23 +537,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { - /* - * six 0s are appended to the lsb of each threshold value - * internally in h/w. - * Only 8 bits are allowed for programming RcBufThreshold - */ - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; - } - - /* - * For 6bpp, RC Buffer threshold 12 and 13 need a different value - * as per C Model - */ - if (compressed_bpp == 6) { - vdsc_cfg->rc_buf_thresh[12] = 0x7C; - vdsc_cfg->rc_buf_thresh[13] = 0x7D; - } + drm_dsc_set_rc_buf_thresh(vdsc_cfg); /* * From XE_LPD onwards we supports compression bpps in steps of 1 diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 8b41edbbabab..706ba1d34742 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); #endif /* _DRM_DSC_HELPER_H_ */