From patchwork Thu Mar 30 21:52:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 668651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC465C77B6E for ; Thu, 30 Mar 2023 21:54:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230181AbjC3VyH (ORCPT ); Thu, 30 Mar 2023 17:54:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230030AbjC3VyG (ORCPT ); Thu, 30 Mar 2023 17:54:06 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EEDC10431 for ; Thu, 30 Mar 2023 14:54:04 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id t14so21123776ljd.5 for ; Thu, 30 Mar 2023 14:54:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680213242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mFApzfWNsAwmB3vyQE6sFojRqTocqp5Twuv0V0PgS64=; b=jvFGNpwNZ9BHGb6Lqi8cVIL1Y1ZjAOzFtxqpesGJgvpx+gCKUmNq510sGvNq/KlwGp koY1WnREAp4O9QWLEG69bc/ix2eIw24DhnUn0uHDoBo0kyQFOygXhMaosiUzQ7TpruI+ CWNFZUmYF5EwLELh4Ansi28lm7YpKoqZj9y9nrkw+Nyd4MYKWZM/gylaHatC9IwSnsDZ AzX9q0hVFLK/+WYsLaNGhJTtuafZrlQ+mlSPbWZvrApW57RhSfTlQ0hMeYmQ8glqOm5w +jtTWPd62UPU5wNnRuqqkIkssW3emmIcJGWngbyp1jBvZIi1pcF3FiEyF0EcfWkKPtti McOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680213242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mFApzfWNsAwmB3vyQE6sFojRqTocqp5Twuv0V0PgS64=; b=cNY0ef+E3aEPIjpYlFQVB1OznpyFSkyzIo15z93xYd4qHKpjFxTf2RJCZZ4bjH1baB f405kIsg52j2gyMKR3Xa1X3F6H+DRNrtrp3EZSHDJUIZkm0edfdIBv4RdMkXFI1tnbq4 PR9Rybd6W02uOV5bo1/H/lxvt3ggEw8Cm8xRBZn4j/3otq7UfB4xkdNeeVgb4szvCH0f xayr7EMuohfmlN9jFVvF0LqpUn9AiqKaRfjK2+3Xvxzcrkfo5RH25zjOFh+zTcwxX6yr xsGhf5aFM9JLV4UrC9A98rdyda9OGzDIy55F1WAxB1ZZrwSysTduMHTdcy5MuluFifEh 9XyA== X-Gm-Message-State: AAQBX9e/H2knfgqTIvtxsaBdxGL8OMDX/57VoRlfS7iTgJmA3qpS3UU6 oo+2V8GpivXKNgcYC8y7i+fZIQ== X-Google-Smtp-Source: AKy350buX2KWEkr7V9m3d57g6JfhCKlaOYhnecqKTUdH+go4JLJUGkbVLwL9q9+JUGayzM2r1S63iQ== X-Received: by 2002:a2e:b709:0:b0:295:b2a0:498a with SMTP id j9-20020a2eb709000000b00295b2a0498amr7842074ljo.13.1680213242609; Thu, 30 Mar 2023 14:54:02 -0700 (PDT) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id f16-20020a056512093000b004cc8207741fsm104574lft.93.2023.03.30.14.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 14:54:02 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio Subject: [PATCH v3 10/38] drm/msm/dpu: split SM6115 catalog entry to the separate file Date: Fri, 31 Mar 2023 00:52:56 +0300 Message-Id: <20230330215324.1853304-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230330215324.1853304-1-dmitry.baryshkov@linaro.org> References: <20230330215324.1853304-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 95 +++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 89 +---------------- 2 files changed, 97 insertions(+), 87 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h new file mode 100644 index 000000000000..f6db2d42a0ed --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_6_3_SM6115_H +#define _DPU_6_3_SM6115_H + +static const struct dpu_caps sm6115_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages = 0x4, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth = 2160, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_10, + .highest_bank_bit = 0x1, + .ubwc_swizzle = 0x7, +}; + +static const struct dpu_mdp_cfg sm6115_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + }, +}; + +static const struct dpu_sspp_cfg sm6115_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), +}; + +static const struct dpu_perf_cfg sm6115_perf_data = { + .max_bw_low = 3100000, + .max_bw_high = 4000000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xff, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +static const struct dpu_mdss_cfg sm6115_dpu_cfg = { + .caps = &sm6115_dpu_caps, + .ubwc = &sm6115_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sm6115_mdp), + .mdp = sm6115_mdp, + .ctl_count = ARRAY_SIZE(qcm2290_ctl), + .ctl = qcm2290_ctl, + .sspp_count = ARRAY_SIZE(sm6115_sspp), + .sspp = sm6115_sspp, + .mixer_count = ARRAY_SIZE(qcm2290_lm), + .mixer = qcm2290_lm, + .dspp_count = ARRAY_SIZE(qcm2290_dspp), + .dspp = qcm2290_dspp, + .pingpong_count = ARRAY_SIZE(qcm2290_pp), + .pingpong = qcm2290_pp, + .intf_count = ARRAY_SIZE(qcm2290_intf), + .intf = qcm2290_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sm6115_perf_data, + .mdss_irqs = IRQ_SC7180_MASK, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 355952eb59ea..5f5daf46fa7f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -366,16 +366,6 @@ static const struct dpu_caps sc7180_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_caps sm6115_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, - .max_mixer_blendstages = 0x4, - .qseed_type = DPU_SSPP_SCALER_QSEED4, - .has_dim_layer = true, - .has_idle_pc = true, - .max_linewidth = 2160, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - static const struct dpu_caps sm8150_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, @@ -435,12 +425,6 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = { .highest_bank_bit = 0x3, }; -static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_10, - .highest_bank_bit = 0x1, - .ubwc_swizzle = 0x7, -}; - static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = { .ubwc_version = DPU_HW_UBWC_VER_30, .highest_bank_bit = 0x2, @@ -551,18 +535,6 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = { }, }; -static const struct dpu_mdp_cfg sm6115_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x494, - .features = 0, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2ac, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2ac, .bit_off = 8}, - }, -}; - static const struct dpu_mdp_cfg sm8250_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -898,13 +870,6 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_cfg sm6115_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, - sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), -}; - static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = @@ -1679,35 +1644,6 @@ static const struct dpu_perf_cfg sc7180_perf_data = { .bw_inefficiency_factor = 120, }; -static const struct dpu_perf_cfg sm6115_perf_data = { - .max_bw_low = 3100000, - .max_bw_high = 4000000, - .min_core_ib = 2400000, - .min_llcc_ib = 800000, - .min_dram_ib = 800000, - .min_prefill_lines = 24, - .danger_lut_tbl = {0xff, 0xffff, 0x0}, - .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc7180_qos_linear), - .entries = sc7180_qos_linear - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - /* TODO: macrotile-qseed is different from macrotile */ - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - static const struct dpu_perf_cfg sm8150_perf_data = { .max_bw_low = 12800000, .max_bw_high = 12800000, @@ -1894,29 +1830,6 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = { .mdss_irqs = IRQ_SC7180_MASK, }; -static const struct dpu_mdss_cfg sm6115_dpu_cfg = { - .caps = &sm6115_dpu_caps, - .ubwc = &sm6115_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sm6115_mdp), - .mdp = sm6115_mdp, - .ctl_count = ARRAY_SIZE(qcm2290_ctl), - .ctl = qcm2290_ctl, - .sspp_count = ARRAY_SIZE(sm6115_sspp), - .sspp = sm6115_sspp, - .mixer_count = ARRAY_SIZE(qcm2290_lm), - .mixer = qcm2290_lm, - .dspp_count = ARRAY_SIZE(qcm2290_dspp), - .dspp = qcm2290_dspp, - .pingpong_count = ARRAY_SIZE(qcm2290_pp), - .pingpong = qcm2290_pp, - .intf_count = ARRAY_SIZE(qcm2290_intf), - .intf = qcm2290_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .perf = &sm6115_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, -}; - static const struct dpu_mdss_cfg sm8150_dpu_cfg = { .caps = &sm8150_dpu_caps, .ubwc = &sm8150_ubwc_cfg, @@ -2025,6 +1938,8 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = { .mdss_irqs = IRQ_SC7180_MASK, }; +#include "catalog/dpu_6_3_sm6115.h" + #include "catalog/dpu_7_0_sm8350.h" #include "catalog/dpu_7_2_sc7280.h"