From patchwork Mon Mar 27 12:53:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 668296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80894C761A6 for ; Mon, 27 Mar 2023 12:53:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232582AbjC0Mxf (ORCPT ); Mon, 27 Mar 2023 08:53:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232356AbjC0MxZ (ORCPT ); Mon, 27 Mar 2023 08:53:25 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32FB110FA for ; Mon, 27 Mar 2023 05:53:23 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id u1so4971880wmn.5 for ; Mon, 27 Mar 2023 05:53:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1679921601; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OsAcKkkhh2xD0zEWe6Y/fbdCXDRgje0cU2EbheBpM/A=; b=xoksPbxKdJsNHfgM5QsaVFidtL/2Bq+iWgoRNetfXf9KMlnl6mJf8eDW3s/BtfdbX9 PCt+UnfcWvonQnK+4LcnehnHy/WpSTF7FFh48JYdgzPzQruyYU8WoHDnaUcudrSbHRn4 7PTqf+U763p3cydt7FmbGxmGpP6DhklPtysaM2OscbbSoyq+u744zJYHfExgMxLhRk2E DoVk8O3Nyn6n4qzGKWZqDGtswsSCPQwefixJdW9SJa0KznLh+6jP2ftWi75h0tmAftKT cNdXMP0bEFZVRNd0UoC/pjgwMiLhJxdcPQnfwMd+/JOVmuBrNI9gT+pwytaHkjCwank3 O1yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921601; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OsAcKkkhh2xD0zEWe6Y/fbdCXDRgje0cU2EbheBpM/A=; b=dm6U3KDL9J/SK0ViKDKAOLL2aVjeFuxfUzDcJgqMpUnwkX0nSW1K2aIRNa3nCFyp4o BbmOvJrDEEd4R/0ZxCHcz3CRteFQKh0sRoo38wchBIdk6QCzknmBIZ2DU9RAsfNxem+E T+hPfCIpHfCb0dG8JlmORJeqtb5oHYPXYGi1W+brd3al60rCRWDR0xemelWVDUuDrEMJ DJPWArhXn2vNMgnHnGwhdLuZSZLZBcmFJ17ch4DLHNp+f8Tf9iUDciLTgdPRDjRqOSFx M+wYxeULMhdOOr7VuQZ99dV+jHnbROmIysl+464pFcgCbVJbxlyQsCKEV1G4+qka6B69 2ubg== X-Gm-Message-State: AO0yUKVUnx8nQgMlxQCqP5A6yX8grokULoADaOFO1l17AG8Qk9q9Mh8e yiIp2gNaPvsVnrl8P3ebbIjJew== X-Google-Smtp-Source: AK7set/2d6R65fkSCinPsHucKuonJMyNpgCFkbo5jXe3E16ZX8HxQ+b6Hkl8TlAxJG2xOI4PKy/xyA== X-Received: by 2002:a7b:c38a:0:b0:3ed:276d:81a4 with SMTP id s10-20020a7bc38a000000b003ed276d81a4mr9319532wmj.32.1679921601703; Mon, 27 Mar 2023 05:53:21 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:313d:a304:2790:a949]) by smtp.gmail.com with ESMTPSA id q25-20020a1ce919000000b003ee58e8c971sm13572220wmc.14.2023.03.27.05.53.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:53:21 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v3 02/18] arm64: dts: qcom: sa8775p: sort soc nodes by reg property Date: Mon, 27 Mar 2023 14:53:00 +0200 Message-Id: <20230327125316.210812-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230327125316.210812-1-brgl@bgdev.pl> References: <20230327125316.210812-1-brgl@bgdev.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bartosz Golaszewski Sort all children of the soc node by the first address in their reg property. This was mostly already the case but there were some nodes that didn't follow it so fix it now for consistency. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 394 +++++++++++++------------- 1 file changed, 197 insertions(+), 197 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 5aa28a3b12ae..296ba69b81ab 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -471,50 +471,6 @@ ipcc: mailbox@408000 { #mbox-cells = <2>; }; - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x443 0x0>; - status = "disabled"; - - uart10: serial@a8c000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00a8c000 0x0 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - interconnect-names = "qup-core", "qup-config"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 - &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QUP_1 0>; - power-domains = <&rpmhpd SA8775P_CX>; - operating-points-v2 = <&qup_opp_table_100mhz>; - status = "disabled"; - }; - - uart12: serial@a94000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00a94000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - power-domains = <&rpmhpd SA8775P_CX>; - status = "disabled"; - }; - }; - qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -585,173 +541,56 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, }; }; - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - }; - - memtimer: timer@17c20000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - ranges = <0x0 0x0 0x0 0x20000000>; - #address-cells = <1>; - #size-cells = <1>; - - frame@17c21000 { - reg = <0x17c21000 0x1000>, - <0x17c22000 0x1000>; - interrupts = , - ; - frame-number = <0>; - }; - - frame@17c23000 { - reg = <0x17c23000 0x1000>; - interrupts = ; - frame-number = <1>; - status = "disabled"; - }; - - frame@17c25000 { - reg = <0x17c25000 0x1000>; - interrupts = ; - frame-number = <2>; - status = "disabled"; - }; - - frame@17c27000 { - reg = <0x17c27000 0x1000>; - interrupts = ; - frame-number = <3>; - status = "disabled"; - }; - - frame@17c29000 { - reg = <0x17c29000 0x1000>; - interrupts = ; - frame-number = <4>; - status = "disabled"; - }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x443 0x0>; + status = "disabled"; - frame@17c2b000 { - reg = <0x17c2b000 0x1000>; - interrupts = ; - frame-number = <5>; + uart10: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; - frame@17c2d000 { - reg = <0x17c2d000 0x1000>; - interrupts = ; - frame-number = <6>; + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; }; - apps_rsc: rsc@18200000 { - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - label = "apps_rsc"; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sa8775p-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board_clk>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sa8775p-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp-0 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp-1 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp-4 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp-5 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp-6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp-7 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp-8 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp-9 { - opp-level = ; - }; - }; - }; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; }; - cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,sa8775p-cpufreq-epss", - "qcom,cpufreq-epss"; - reg = <0x0 0x18591000 0x0 0x1000>, - <0x0 0x18593000 0x0 0x1000>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>; @@ -900,6 +739,167 @@ apps_smmu: iommu@15000000 { , ; }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + memtimer: timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c27000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sa8775p-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sa8775p-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level = ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sa8775p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; arch_timer: timer {