From patchwork Fri Mar 24 02:25:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 666619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CC11C77B6D for ; Fri, 24 Mar 2023 02:25:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231388AbjCXCZ6 (ORCPT ); Thu, 23 Mar 2023 22:25:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231489AbjCXCZ4 (ORCPT ); Thu, 23 Mar 2023 22:25:56 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2F0B11666 for ; Thu, 23 Mar 2023 19:25:54 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id c29so417789lfv.3 for ; Thu, 23 Mar 2023 19:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679624753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d/gnfsKFbcAyu+OZx2h2K2YsHO/72DkLTZ3N8dlKvBs=; b=dJm9nKDwcPwPQ5u8UkiR+ilig2pjarnv5cjfV589TVIk1SLCEy+JT4stpde7wVpQ1r YXx5YEy/52a5swh1qDFMuQoS05k1YsB6xXwFS05WxGqsm3Ydprl1c4o6eMA3U68nA3uw eWwv5YLW1hdKrJU4AFo9TK6Lo9RBVB8us8ZbMecD/ZXrvNyF9G3KpfByhpzXzxWBlLqc reNmbHawGLVvvn+pyYQRne8e1Dybf2Dfj9i0AOLvg1x57Zn4RGrYOcY+fiQoWYJHdfWX 6XdS1UwkBBOgpoqOCLVwiVFMdZclgayNxMsj5NxXoPvD5qiuwNU5Gs+Ti6NHUOn9E+S9 IFIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679624753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d/gnfsKFbcAyu+OZx2h2K2YsHO/72DkLTZ3N8dlKvBs=; b=6OvSOZIEcN4UJ8itgabYIMg994HFup2YY/5h3/4G9iJjUNsa0IKeojN9Ih0feQUXCx z9aH4559FIZd2WUFRx5MaIptdL59Lpo6tO2XlKUfAc+zbTC/aurcit0Rn9uuAMS+vVEc W5Ku1+TeX00W51x3rI2fuzOVh5/MROE3JCNgRk+26kBPx3/OGOZY1P+MzcueB+C2ScxM EDstY7h2zyEYLS9RXzNQACuHX6HZ6hYtWI1PD1KU9hJog8sc6HoMBw8QvV+qDkUoY846 QezqilepLIzdjELDhjE11/yWD1w8rGJg/QF5cgTysC9uNcSbycoa3scgUY1F1iyFZagw hnyA== X-Gm-Message-State: AAQBX9fn+MpE+3/sCrfTrnkDAijPTeOWf32D3hl/2f8BbddreznpjW7G ojJ0YoaEU3zU5MAoHFR3PKw0QVg2MKrv1k8cLvXFMw== X-Google-Smtp-Source: AKy350bujY7U2l6HRhUWB9tQ1GyvocnORtQs1tjP1kgU5w8AVu3DVjmKftcm9jN9UoAmGOCsiI0kvw== X-Received: by 2002:ac2:50d9:0:b0:4e0:54a3:4b3b with SMTP id h25-20020ac250d9000000b004e054a34b3bmr242703lfm.69.1679624753182; Thu, 23 Mar 2023 19:25:53 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x4-20020a19f604000000b004db3aa3c542sm3162628lfe.47.2023.03.23.19.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 19:25:52 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Johan Hovold Subject: [PATCH 36/41] arm64: dts: qcom: sm8150: switch PCIe QMP PHY to new style of bindings Date: Fri, 24 Mar 2023 05:25:09 +0300 Message-Id: <20230324022514.1800382-37-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230324022514.1800382-1-dmitry.baryshkov@linaro.org> References: <20230324022514.1800382-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 66 +++++++++++----------------- 1 file changed, 26 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index be10b68893e8..e4ecc0804cd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1859,7 +1859,7 @@ pcie0: pci@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie0_phy>; phy-names = "pciephy"; perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; @@ -1873,14 +1873,20 @@ pcie0: pci@1c00000 { pcie0_phy: phy@1c06000 { compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; - reg = <0 0x01c06000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c06000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "refgen"; + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "refgen", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -1889,18 +1895,6 @@ pcie0_phy: phy@1c06000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie0_lane: phy@1c06200 { - reg = <0 0x01c06200 0 0x170>, /* tx */ - <0 0x01c06400 0 0x200>, /* rx */ - <0 0x01c06800 0 0x1f0>, /* pcs */ - <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; }; pcie1: pci@1c08000 { @@ -1958,7 +1952,7 @@ pcie1: pci@1c08000 { power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; @@ -1972,14 +1966,20 @@ pcie1: pci@1c08000 { pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; - reg = <0 0x01c0e000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c0e000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "refgen"; + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "refgen", + "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -1988,20 +1988,6 @@ pcie1_phy: phy@1c0e000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c0e200 { - reg = <0 0x01c0e200 0 0x170>, /* tx0 */ - <0 0x01c0e400 0 0x200>, /* rx0 */ - <0 0x01c0ea00 0 0x1f0>, /* pcs */ - <0 0x01c0e600 0 0x170>, /* tx1 */ - <0 0x01c0e800 0 0x200>, /* rx1 */ - <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; }; ufs_mem_hc: ufshc@1d84000 {