From patchwork Tue Mar 21 01:18:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 665610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6A54C6FD1C for ; Tue, 21 Mar 2023 01:20:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230379AbjCUBUM (ORCPT ); Mon, 20 Mar 2023 21:20:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230454AbjCUBUK (ORCPT ); Mon, 20 Mar 2023 21:20:10 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F087C5268 for ; Mon, 20 Mar 2023 18:19:42 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id x17so17235017lfu.5 for ; Mon, 20 Mar 2023 18:19:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679361508; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C0ShU0VoJuNaKygLaJG1lCz4q0jlhQ8mz6XNRmWcdJs=; b=UI5Ui7wIUM7KtMV4pcooX6Nn/8MkGfdhXRxKsQ/k3AePUCwncAf/AwCNyKfeTeM6/g E/JIuhFwkJ/rgtoakBIl1E0c/rLsGzykagu4tEJMBljxXYkdjikkMMfq0fTT625tWxiR iLPA5AuTcS3DbBDPV6ZhsTF3FCrWEav+U+X6fvanp6D/Ympw/cT/7zLIubM+bGlTAr4u 9kp7WrM9hHOArJ7R56wiRaDxdB3AwMiVoRtqg5UGsTOoJCv7OlilwadkK284cVkYfxdJ HgPooFcRvHVovMM89YccsTlsnarAmZv2Wmm81qEvXBoVmmXzqHdsjy+rqzjk8FQMNWeK NWag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679361508; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C0ShU0VoJuNaKygLaJG1lCz4q0jlhQ8mz6XNRmWcdJs=; b=YfE8SuoBcwqXJRD8kfyDOONkwEF5JuLMVCcWYdSeToKOQqfaytzLc4Aeq4BffnE/vy E82aqaPjNK4Jhxsssh2boTfjx116qf53mPflbW7gekeOJCMB5Vb5C/oiH2IsId1Hdbiw guzOL219GVYS0xYLroAZzx3XCnodq8ny9PnzZ7+ZxC/K4Ntm4Yf/fHUEoiCVjAgiT7hC rYMxWOkLZuDdrSNWFzlVcZT0xgwN8kOY6iUWee/qJ6y6/pOpDlHfugvNQzAGnN2eMtYM YzQ9wzWvTvmC1GTdGvFK4jJCHyJmZrbAVD6/tYH+YvT7Edh8fIzHp11wJXWZTvI4OOsI T2XA== X-Gm-Message-State: AO0yUKXC7SpSR3SajZlOWgZzdY6hSx23lpWlHyEFO9Jk1rqfVv5vxhq5 PsGiG4BJjAUQZtqT1caz4ZN6xw== X-Google-Smtp-Source: AK7set+qhT3VjPfVMqjX4XLHYsAFppTsFoCQcM9asYTAdkeMztSusgLS5MmLSoqvzQVakb5gi/AU7g== X-Received: by 2002:ac2:5151:0:b0:4ea:e640:2a58 with SMTP id q17-20020ac25151000000b004eae6402a58mr335231lfd.42.1679361508504; Mon, 20 Mar 2023 18:18:28 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c18-20020ac25312000000b004eaec70c68esm46863lfh.294.2023.03.20.18.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 18:18:28 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [RFC PATCH v2 08/13] drm/msm/dpu: fill CRTC resources in dpu_crtc.c Date: Tue, 21 Mar 2023 04:18:16 +0300 Message-Id: <20230321011821.635977-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230321011821.635977-1-dmitry.baryshkov@linaro.org> References: <20230321011821.635977-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources from dpu_crtc_assign_resources(). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 27 +++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 24 ++---------------- 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 77226de54363..8ef191fd002d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1177,6 +1177,7 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) } #define MAX_HDISPLAY_SPLIT 1080 +#define MAX_CHANNELS_PER_CRTC 2 static struct msm_display_topology dpu_crtc_get_topology( struct drm_crtc *crtc, @@ -1219,9 +1220,14 @@ static struct msm_display_topology dpu_crtc_get_topology( static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { + struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_CRTC]; + struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_CRTC]; + int i, num_lm, num_ctl, num_dspp; struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); struct dpu_global_state *global_state; struct msm_display_topology topology; + struct dpu_crtc_state *cstate; int ret; /* @@ -1243,6 +1249,27 @@ static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_stat if (ret) return ret; + cstate = to_dpu_crtc_state(crtc_state); + + num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + crtc, DPU_HW_BLK_DSPP, hw_dspp, + ARRAY_SIZE(hw_dspp)); + + for (i = 0; i < num_lm; i++) { + int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); + + cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); + cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); + if (i < num_dspp) + cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); + } + + cstate->num_mixers = num_lm; + return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 204360485b81..068d4e47eaa9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -934,14 +934,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, struct dpu_encoder_virt *dpu_enc; struct msm_drm_private *priv; struct dpu_kms *dpu_kms; - struct dpu_crtc_state *cstate; struct dpu_global_state *global_state; struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; - int num_lm, num_ctl, num_pp, num_dsc; + int num_pp, num_dsc; unsigned int dsc_mask = 0; int i; @@ -968,13 +965,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, ARRAY_SIZE(hw_pp)); - num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); - num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_DSPP, hw_dspp, - ARRAY_SIZE(hw_dspp)); + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) @@ -992,18 +984,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, dpu_enc->dsc_mask = dsc_mask; - cstate = to_dpu_crtc_state(crtc_state); - - for (i = 0; i < num_lm; i++) { - int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); - - cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); - cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); - cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); - } - - cstate->num_mixers = num_lm; - dpu_enc->connector = conn_state->connector; for (i = 0; i < dpu_enc->num_phys_encs; i++) {