From patchwork Wed Mar 15 06:42:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 663548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C7D1C76196 for ; Wed, 15 Mar 2023 06:43:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231351AbjCOGnY (ORCPT ); Wed, 15 Mar 2023 02:43:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231384AbjCOGnU (ORCPT ); Wed, 15 Mar 2023 02:43:20 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CDCD23649 for ; Tue, 14 Mar 2023 23:43:19 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id a2so19023971plm.4 for ; Tue, 14 Mar 2023 23:43:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678862598; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3tT4IStfyTS7c0lPgVozml2BSLbP+qQslzAxoVdPoGM=; b=EN8Lhco9aE1qbc4UoyfWKIRwRfiLncmoXFTc/KBlI474QMotBP/MLiW0nUTSxrUtUz CJfox4hg2RE3XhdLhp4OfEUnW6J5nL40/YQ/RvBiPlVJq/NXG6/0pbryIktGiY2CLikK SvZ8lkvpIMlRhqoCNRGmPLxZX3/ttS5kcGrKEx/ZbAsD4gmOG17y0xmWPi8o6piw+rs8 TD+N+lksTYKL8k050GNt3NU16T9RYVt0oztjlGD/R7bwqcV1K5DfGeIFjURMQlY439KZ IxSFc6tSFc0hzGSrVp5dPbyo3tuKWRFdK4BjfQ+Y0mTgkSCEacWGyQeudY4f2WMy54zu moxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678862598; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3tT4IStfyTS7c0lPgVozml2BSLbP+qQslzAxoVdPoGM=; b=DQ55BUHb2mdEXPuTFGYN+myr4payvhn7watKyO6p7/6r3wxsvfBP4Kh15r6H7zJiXq PfPqmmjKxzGfpqoOlnh+CRppKniQRP4Lu/sdazl+jNFKUUOnBwZWSQPO1deChNHHsEIa vwGFLJPDBMa3ZAbMFVqtP6nSGq+QBfb3OgemmnqwZhWmRm5FDs7nTBBGj8Cicm9hPdPe SOVbhL8wHEqfpgNt6E3LNjti+ZvREiZvmPRVNgo+/z8lhjA+G4AKjjxu+WeGoZ5gHA9x AY/OBgBeTmSb2FRhcWoorWDwLIaVmAsqUT2/ruePlgkhZ1QktzDRwTt0rK/fL3xRvM4m q47w== X-Gm-Message-State: AO0yUKUYOJqdTuLg/HWoW8HWw4jHszkj/cL/DVvrBwvKe5JS811GAM4I WPS/5NU3EfeZ4SNmuLhChLzA X-Google-Smtp-Source: AK7set+AFa+5So49M8YkU2bCePUSACMm/bIcNkBDUageNKvgVgLl8eGW1LDKR0x8+YuHViX9v38iGQ== X-Received: by 2002:a17:90a:4b46:b0:23b:4f4c:a8b with SMTP id o6-20020a17090a4b4600b0023b4f4c0a8bmr11557795pjl.11.1678862598698; Tue, 14 Mar 2023 23:43:18 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.35]) by smtp.gmail.com with ESMTPSA id u4-20020a17090a6a8400b002367325203fsm550747pjj.50.2023.03.14.23.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 23:43:17 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 03/18] PCI: qcom: Use bitfield definitions for register fields Date: Wed, 15 Mar 2023 12:12:40 +0530 Message-Id: <20230315064255.15591-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315064255.15591-1-manivannan.sadhasivam@linaro.org> References: <20230315064255.15591-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To maintain uniformity throughout the driver and also to make the code easier to read, let's make use of bitfield definitions for register fields. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 9223ca76640d..e9f4c70b719a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -76,24 +76,24 @@ #define REQ_NOT_ENTR_L1 BIT(5) /* PARF_PCS_DEEMPH register fields */ -#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x) /* PARF_PCS_SWING register fields */ -#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) -#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) +#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x) +#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x) /* PARF_PHY_CTRL register fields */ #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) -#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x) /* PARF_PHY_REFCLK register fields */ #define PHY_REFCLK_SSP_EN BIT(16) #define PHY_REFCLK_USE_PAD BIT(12) /* PARF_CONFIG_BITS register fields */ -#define PHY_RX0_EQ(x) ((x) << 24) +#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) /* PARF_SLV_ADDR_SPACE_SIZE register value */ #define SLV_ADDR_SPACE_SZ 0x10000000