From patchwork Fri Mar 10 00:56:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 661766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C03BEC6FD1F for ; Fri, 10 Mar 2023 00:57:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229956AbjCJA5e (ORCPT ); Thu, 9 Mar 2023 19:57:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229823AbjCJA53 (ORCPT ); Thu, 9 Mar 2023 19:57:29 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C9D1116C0A for ; Thu, 9 Mar 2023 16:57:18 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id bi9so4628463lfb.2 for ; Thu, 09 Mar 2023 16:57:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678409837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9A1yItHnVjLCkkrvFzWKL06/fFB2ivnHBT1T8+CFDyw=; b=hqNtdpeN0qA/VDzX+xaYgXdG1SGV4mkzKGwKdgAEzTbRbplqCdlOHjIt9wsuvDGXLq dp6/6cutFqLqDcgWGUj+9By9Eaie6E9b10xw/CWCbECapkvakU07fWIcS8vjPDixbD3j yOufhnQ7wbQqP0nlwjINmC3uMc4Mm2lrPz1fhFOSagyrjRyVML68MhVa+jopN9tO4aXX nLzKA2swfO2UxqQbPY1UTVr48jRGwC5VzDcvWthc41b8ZfSTeAfrv70x7bBmzRnJaskS GPiAHozg3aAjmX9FO5rikOhhxMM5hZ37uJ+nFhJ+dp1QsKUWkPfDJinSDRlpAxS2MjNN WNew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678409837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9A1yItHnVjLCkkrvFzWKL06/fFB2ivnHBT1T8+CFDyw=; b=ZQufPUqms/7F7w2WS2ivEV5V00YFpAnwIJfnh2kBETp5Py6v3lrfDdUU2EfgGNHkhu nZHsJIxY4IxpOenYUkBb50NABkkAfRZWkjmJMxvRfQHTQU3ua2iyaic3Hbj1gepvdIuh 30A5xJA9UDTAIgD3mt7ugY21pOiAdi9uSBSTtaf1O/U8Canf6E5p9OfeF1F98Crfm3u7 /JlupNaJLb5JlcmD18Ebkehxjd9AsJ6eiIlvJ5ENzb3a642r5Qg9KlQxspu5Kxr+eeAi M6VBHpM8Rtsuu/18nbZi/yhTBrTSec8ftC74OQsnKtU04ZadCPq6SWE7+2Mo07e1HFQ1 HQ4A== X-Gm-Message-State: AO0yUKW5yPywJ0whqwT4aPzRSUgEMdeCYo3w4Kpiam4YEToICCInJodj WWAatZJxUnoxtWlTifTr2DiC9A== X-Google-Smtp-Source: AK7set8PF3o93TT82oaIRMCY/7HXjV3rnm1RFw71tbPGgfwLNNSXTr0cds2GA5c1spUaRPlphlvLfA== X-Received: by 2002:ac2:533c:0:b0:4dd:a7fb:1e7c with SMTP id f28-20020ac2533c000000b004dda7fb1e7cmr7447177lfh.3.1678409837022; Thu, 09 Mar 2023 16:57:17 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id m13-20020ac2428d000000b004d8540b947asm75280lfh.56.2023.03.09.16.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 16:57:16 -0800 (PST) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v5 13/32] drm/msm/dpu: rename dpu_hw_sspp_cfg to dpu_sw_pipe_cfg Date: Fri, 10 Mar 2023 02:56:45 +0200 Message-Id: <20230310005704.1332368-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310005704.1332368-1-dmitry.baryshkov@linaro.org> References: <20230310005704.1332368-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As struct dpu_hw_sspp_cfg describes only the source and destination rectangles, it is a software pipe configuration now. Rename it accordingly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 ++++++++-------- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index e87c6377f315..6e5b62f3276f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -447,7 +447,7 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) * dpu_hw_sspp_setup_rects() */ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, - struct dpu_hw_sspp_cfg *cfg) + struct dpu_sw_pipe_cfg *cfg) { struct dpu_hw_sspp *ctx = pipe->sspp; struct dpu_hw_blk_reg_map *c; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 100d8e06c90d..e73d6ac863ad 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -153,12 +153,12 @@ struct dpu_hw_pixel_ext { }; /** - * struct dpu_hw_sspp_cfg : SSPP configuration + * struct dpu_sw_pipe_cfg : software pipe configuration * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. */ -struct dpu_hw_sspp_cfg { +struct dpu_sw_pipe_cfg { struct drm_rect src_rect; struct drm_rect dst_rect; }; @@ -228,7 +228,7 @@ struct dpu_hw_sspp_ops { * @cfg: Pointer to pipe config structure */ void (*setup_rects)(struct dpu_sw_pipe *pipe, - struct dpu_hw_sspp_cfg *cfg); + struct dpu_sw_pipe_cfg *cfg); /** * setup_pe - setup pipe pixel extension diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 4ae70d21c37a..ce01a602cbc9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -136,7 +136,7 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) */ static void _dpu_plane_calc_bw(struct drm_plane *plane, struct drm_framebuffer *fb, - struct dpu_hw_sspp_cfg *pipe_cfg) + struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane_state *pstate; struct drm_display_mode *mode; @@ -191,7 +191,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, * Result: Updates calculated clock in the plane state. * Clock equation: dst_w * v_total * fps * (src_h / dst_h) */ -static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_sspp_cfg *pipe_cfg) +static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane_state *pstate; struct drm_display_mode *mode; @@ -275,7 +275,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, * @pipe_cfg: Pointer to pipe configuration */ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, - struct drm_framebuffer *fb, struct dpu_hw_sspp_cfg *pipe_cfg) + struct drm_framebuffer *fb, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); @@ -421,7 +421,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, * @pipe_cfg: Pointer to pipe configuration */ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, - struct drm_crtc *crtc, struct dpu_hw_sspp_cfg *pipe_cfg) + struct drm_crtc *crtc, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); @@ -635,7 +635,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, const struct dpu_format *fmt, bool color_fill, - struct dpu_hw_sspp_cfg *pipe_cfg, + struct dpu_sw_pipe_cfg *pipe_cfg, unsigned int rotation) { struct dpu_hw_sspp *pipe_hw = pipe->sspp; @@ -694,7 +694,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, const struct dpu_format *fmt; const struct drm_plane *plane = &pdpu->base; struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); - struct dpu_hw_sspp_cfg pipe_cfg; + struct dpu_sw_pipe_cfg pipe_cfg; DPU_DEBUG_PLANE(pdpu, "\n"); @@ -1130,9 +1130,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) bool is_rt_pipe; const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(fb)); - struct dpu_hw_sspp_cfg pipe_cfg; + struct dpu_sw_pipe_cfg pipe_cfg; - memset(&pipe_cfg, 0, sizeof(struct dpu_hw_sspp_cfg)); + memset(&pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg)); _dpu_plane_set_scanout(plane, pstate, fb);