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[2/2] arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config

Message ID 20230308183317.559253-2-krzysztof.kozlowski@linaro.org
State New
Headers show
Series [1/2] arm64: dts: qcom: sm8450-hdk: use precise WCD9385 compatible | expand

Commit Message

Krzysztof Kozlowski March 8, 2023, 6:33 p.m. UTC 
Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec
RESET_N reset pin.  It also pulls the pin down in shutdown mode, thus it
is more like a shutdown pin, not a reset.  Use the same settings here
for HDK8450 and keep the WCD9385 by default in powered off (so pin as
low).  Align the name of pin configuration node with other pins in the
DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 9cd1d1bd86cb..4020e54e16f5 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -767,9 +767,11 @@  spkr_2_sd_n_active: spkr-2-sd-n-active-state {
 		output-low;
 	};
 
-	wcd_default: wcd-default-state {
+	wcd_default: wcd-reset-n-active-state {
 		pins = "gpio43";
 		function = "gpio";
+		drive-strength = <16>;
 		bias-disable;
+		output-low;
 	};
 };