From patchwork Fri Mar 3 12:57:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 658524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2C66C7EE2F for ; Fri, 3 Mar 2023 12:57:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230230AbjCCM5t (ORCPT ); Fri, 3 Mar 2023 07:57:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230229AbjCCM5r (ORCPT ); Fri, 3 Mar 2023 07:57:47 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7073D5FE84 for ; Fri, 3 Mar 2023 04:57:45 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id r27so3430567lfe.10 for ; Fri, 03 Mar 2023 04:57:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HuMEa7JmxGfzSNw5Cy7S7gwKFWQp8WlWdvJ9mKz0WfA=; b=NiAOvELOB8FKUnXrh7N4MO7T+/nz5o8b/YVSaZTzyqv5sQa1RU5WW8QBC7rVCh09dO t+7iLUMAWaQ/WgTK2tzaMM0i21U18uSAT1TZHMAFbBIkJFvcI1r8vN/Otw45JLMp5RZF XJE9IM/qf28VSJ6spkwtbggxM/uYqKjS9ABNerrkEDGwLo/1waICBMSR/u6T/aBUfWkD kkcE5GLfy2KJP6X31itGyMytmEtavFwAdfzYN4qNGkRjIwEzWBTkt+/0VGP0Uj9KXTGQ 078ypjKcPsogxq6eESN8ulZbDO81QJfhld+7Ldjv0kF6zcqZDyAw7Fp7DjvjVhQjg/pm UMNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HuMEa7JmxGfzSNw5Cy7S7gwKFWQp8WlWdvJ9mKz0WfA=; b=xmgpWpLyDdT9ua2So0eueBLGDWd2r31U2n5/p0cZ5wfNW3kW1aLUcIk1UIzSTK5elk f32DshqnAFIjt+HRC4W2zEZiSQQ6q+ojv01LbUi/HPWDpiYjqi8GrgjzewtKp+khjJog Wo8GvgOB/bbsxIwS7PeTvRTWqYEtXz3g7RSyWj1UmL31Oxy+GyGMYnxi3vVaj4uoNL6I EIQbLjZvzQkQwpOkiIh11vjZ4frgatEgMmoSs3SpmOVgh2dyLkYSK9wQY8mjtdH2Swv7 3dt5TPHIiDwzat1G62q0696mrg+pX/ayD5vSeBNrFxGNfssD0+2vbeJuytMBcSJUgmt6 EYHw== X-Gm-Message-State: AO0yUKWMr+haNnCJHMkD8H51P3+04VtoI8ZQzvNHgonzItbefswT400o tcLnyN/L9yrfdYcORecXjM+niA== X-Google-Smtp-Source: AK7set9EN5GzqUcNe4e44HBc+aeSbBMaWVrq9gvja0xqmis5UzcTq/oChhIHky+O8YpHU7CQCzuh9g== X-Received: by 2002:ac2:5317:0:b0:4b5:61e8:8934 with SMTP id c23-20020ac25317000000b004b561e88934mr524810lfh.64.1677848263806; Fri, 03 Mar 2023 04:57:43 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c5-20020ac25305000000b004cf07a0051csm379266lfh.228.2023.03.03.04.57.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 04:57:43 -0800 (PST) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 26/30] drm/msm/dpu: split pipe handling from _dpu_crtc_blend_setup_mixer Date: Fri, 3 Mar 2023 14:57:21 +0200 Message-Id: <20230303125725.3695011-27-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230303125725.3695011-1-dmitry.baryshkov@linaro.org> References: <20230303125725.3695011-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework _dpu_crtc_blend_setup_mixer() to split away pipe handling to a separate functon. This is a preparation for the r_pipe support. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 79 +++++++++++++++--------- 1 file changed, 50 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 73e1a8c69ef0..e651e4593280 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -400,6 +400,46 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) } } +static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, + struct drm_plane *plane, + struct dpu_crtc_mixer *mixer, + u32 num_mixers, + enum dpu_stage stage, + struct dpu_format *format, + uint64_t modifier, + struct dpu_sw_pipe *pipe, + unsigned int stage_idx, + struct dpu_hw_stage_cfg *stage_cfg + ) +{ + uint32_t lm_idx; + enum dpu_sspp sspp_idx; + struct drm_plane_state *state; + + sspp_idx = pipe->sspp->idx; + + state = plane->state; + + trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), + state, to_dpu_plane_state(state), stage_idx, + format->base.pixel_format, + modifier); + + DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", + crtc->base.id, + stage, + plane->base.id, + sspp_idx - SSPP_NONE, + state->fb ? state->fb->base.id : -1); + + stage_cfg->stage[stage][stage_idx] = sspp_idx; + stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index; + + /* blend config update */ + for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) + mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx); +} + static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer, struct dpu_hw_stage_cfg *stage_cfg) @@ -412,15 +452,12 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct dpu_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; - uint32_t stage_idx, lm_idx; - int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; + uint32_t lm_idx; bool bg_alpha_enable = false; DECLARE_BITMAP(fetch_active, SSPP_MAX); memset(fetch_active, 0, sizeof(fetch_active)); drm_atomic_crtc_for_each_plane(plane, crtc) { - enum dpu_sspp sspp_idx; - state = plane->state; if (!state) continue; @@ -431,39 +468,21 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, pstate = to_dpu_plane_state(state); fb = state->fb; - sspp_idx = pstate->pipe.sspp->idx; - set_bit(sspp_idx, fetch_active); - - DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", - crtc->base.id, - pstate->stage, - plane->base.id, - sspp_idx - SSPP_VIG0, - state->fb ? state->fb->base.id : -1); - format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; - stage_idx = zpos_cnt[pstate->stage]++; - stage_cfg->stage[pstate->stage][stage_idx] = - sspp_idx; - stage_cfg->multirect_index[pstate->stage][stage_idx] = - pstate->pipe.multirect_index; - - trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), - state, pstate, stage_idx, - format->base.pixel_format, - fb ? fb->modifier : 0); + set_bit(pstate->pipe.sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + mixer, cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe, 0, stage_cfg); /* blend config update */ for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, - pstate, format); - - mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, - sspp_idx); + _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); if (bg_alpha_enable && !format->alpha_enable) mixer[lm_idx].mixer_op_mode = 0; @@ -1297,6 +1316,8 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); + seq_printf(s, "\tsspp:%s\n", + pstate->pipe.sspp->cap->name); seq_printf(s, "\tmultirect: mode: %d index: %d\n", pstate->pipe.multirect_mode, pstate->pipe.multirect_index);