From patchwork Sat Feb 11 02:10:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 652752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5495CC6379F for ; Sat, 11 Feb 2023 02:11:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229611AbjBKCL0 (ORCPT ); Fri, 10 Feb 2023 21:11:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229609AbjBKCL0 (ORCPT ); Fri, 10 Feb 2023 21:11:26 -0500 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C6827534E for ; Fri, 10 Feb 2023 18:11:25 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id sa10so20154569ejc.9 for ; Fri, 10 Feb 2023 18:11:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=peX0Hd3MUbZTRxXaxBuK9erOu86OezHmTR38rFHYkm0=; b=YWm4wbd66ZWAhomKVzJLUsZJNQEcEO7LPzrnKhH1sB55dCVEo2O9sqJGQxPllNHfyM IVjrQgqSddIJTmXF9I0y60RFAh2S5SGVdF4wGWZxZfUKFdue1UHAapr8EnjquPilQ83z d0UGrMh2xZXy1nU0jf08oFtNgmIg3OsBckAVCPXQeXsLyc4Wk6237MYBhYGaZkHPNaln Kp0gzJpoG+CvawSSXSbgVmCK5EroirWWW3Ig+xBjO9Kb2VvqUsSfJJdgM6lKfiUF32NP aq7Nzpah+gSmbuXOs4itqsyCCKFP5Q74kthXPENCz0+3kaCF52bd2tI9PHJ4SjmwuPR9 avJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=peX0Hd3MUbZTRxXaxBuK9erOu86OezHmTR38rFHYkm0=; b=1J4bPucdxyTL8RmNXfNMmvR44/A9MQ85fUL3qn/miKHFaLMkFpQTCxfbEv+iHVW7Zn mjcR2fTxJCvsHl95FYcNps4AXrV9xDnAJew/rqSymexi4lp9eeGK1CO3UqgQwO36cVWX KvgQq3vZltbnaby3PIdK/ERMl0/BHOJtSBDhfUELu+zFvFni7OvBr9x0+F+26vPnnoyg rckrGyZL87dN8bkhbtILKIQPBid2BsFtqoCQLcPR1u6YxrQZ4JMRkIkngXW2JBAazUEC NvZAwaO446KgD5G/hXvML0sIW3+x9Bs5m/m7gbwV4JLSMMK8+NqB3PUWEIoA9z4eaZR9 G1ng== X-Gm-Message-State: AO0yUKVhBVE+1N2sWj9uYO9QGeiA8gdaLfmDWV4WZvAiyvPfE49gpQSY NW5tZDVf4ehrB5ZANl5Lzb2J5g== X-Google-Smtp-Source: AK7set/E1LUGPJmIPCdCkwWyy4/g5rAKo+8SUU3oO4vYg2wRsUwk4sp42J1AVm9rvUdPQ17/Q+Cp2w== X-Received: by 2002:a17:906:3b94:b0:886:4ca1:39f1 with SMTP id u20-20020a1709063b9400b008864ca139f1mr17306559ejf.73.1676081483720; Fri, 10 Feb 2023 18:11:23 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e20-20020a170906c01400b008ae3324c8adsm3180831ejz.214.2023.02.10.18.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 18:11:23 -0800 (PST) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 27/43] drm/msm/dpu: correct sc8280xp scaler Date: Sat, 11 Feb 2023 04:10:37 +0200 Message-Id: <20230211021053.1078648-28-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211021053.1078648-1-dmitry.baryshkov@linaro.org> References: <20230211021053.1078648-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org QSEED4 is a newer variant of QSEED3LITE, which should be used on sc8280xp. Fix the DPU caps structure and used feature masks. Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 10 +++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index a9df4c1a714a..7b0dac12895e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -10,7 +10,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 11, - .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, + .qseed_type = DPU_SSPP_SCALER_QSEED4, .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .has_src_split = true, .has_dim_layer = true, @@ -83,13 +83,13 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = { }; static const struct dpu_sspp_cfg sc8280xp_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK, + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK, + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK, + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 48ee66f52ddc..f3649ac9cc70 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -435,13 +435,13 @@ static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5); static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6); static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 = - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_1 = - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_2 = - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 = - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4); #define _VIG_SBLK_NOSCALE(num, sdma_pri) \ { \