From patchwork Thu Feb 9 01:13:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 652145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9192C636CC for ; Thu, 9 Feb 2023 01:15:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231280AbjBIBPD (ORCPT ); Wed, 8 Feb 2023 20:15:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231273AbjBIBPC (ORCPT ); Wed, 8 Feb 2023 20:15:02 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F84544AF; Wed, 8 Feb 2023 17:15:01 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3191B5M3023926; Thu, 9 Feb 2023 01:14:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=GGCDrD1fRQVfqryQDH4mh5EfzTuBkKy/vEkm/guCnlE=; b=nh0NFJxV781jpUxOZ/zheJQ7zF9/rA5/Lle/srpNOS6PWOgJP2qMF4/K8Blo6FQoyzQD wFwAzUNJ+3o1PhLFSQlOnBXST21rl2RsAYH4gLeLU13+CaaerNaWWn7jFdNFu1ElXajM 0j85OAwBRcYOJXC1GPdaqvbT2Xqf+V97Fmo2tKclADWnUMG3udYneFZKij3F3cPxDqUc MOBC0Tpp3yOxotf4yefcn4yWUy5jwv++qV7Lw2kh5jETE7VuiErlkafFLO4NiSqWiAcV EqBOB1VsXBa+o1xGZjGZkJVeT73nUn47DMBGE0SqoW7EYTJqsqrcVh4EUt5zacZhhxPr 1Q== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3nmpte00qa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Feb 2023 01:14:47 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3191Ei1W015201 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 9 Feb 2023 01:14:46 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 17:14:37 -0800 From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Konrad Dybcio CC: Rob Herring , Krzysztof Kozlowski , Catalin Marinas , Will Deacon , , , , Subject: [PATCH v2 1/4] arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks Date: Wed, 8 Feb 2023 17:13:22 -0800 Message-ID: <20230209011325.2603663-2-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209011325.2603663-1-quic_bjorande@quicinc.com> References: <20230209011325.2603663-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: KBOUpnqa27xb8QHoblXhW12aBeI8QaCJ X-Proofpoint-ORIG-GUID: KBOUpnqa27xb8QHoblXhW12aBeI8QaCJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-08_11,2023-02-08_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302090009 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson Add the two DisplayPort controllers that are attached to QMP phys for providing display output on USB Type-C. Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson --- Changes since v1: - None arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 170 ++++++++++++++++++++++++- 1 file changed, 166 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index dceb7eb3106b..fcd393444f47 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3155,6 +3155,20 @@ ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + mdss0_intf0_out: endpoint { + remote-endpoint = <&mdss0_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + mdss0_intf4_out: endpoint { + remote-endpoint = <&mdss0_dp1_in>; + }; + }; + port@5 { reg = <5>; mdss0_intf5_out: endpoint { @@ -3199,6 +3213,154 @@ opp-600000000 { }; }; + mdss0_dp0: displayport-controller@ae90000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss0>; + interrupts = <12>; + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss0_dp0_opp_table>; + power-domains = <&rpmhpd SC8280XP_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dp0_in: endpoint { + remote-endpoint = <&mdss0_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss0_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss0_dp1: displayport-controller@ae98000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xae98000 0 0x200>, + <0 0xae98200 0 0x200>, + <0 0xae98400 0 0x600>, + <0 0xae99000 0 0x400>, + <0 0xae99400 0 0x400>; + interrupt-parent = <&mdss0>; + interrupts = <13>; + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss0_dp1_opp_table>; + power-domains = <&rpmhpd SC8280XP_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dp1_in: endpoint { + remote-endpoint = <&mdss0_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss0_dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss0_dp2: displayport-controller@ae9a000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0xae9a000 0 0x200>, @@ -3387,10 +3549,10 @@ dispcc0: clock-controller@af00000 { clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, - <0>, - <0>, - <0>, + <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>, <&mdss0_dp3_phy 0>,