From patchwork Wed Feb 8 18:00:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 652990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A2C2C05027 for ; Wed, 8 Feb 2023 18:01:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232085AbjBHSBa (ORCPT ); Wed, 8 Feb 2023 13:01:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231717AbjBHSBO (ORCPT ); Wed, 8 Feb 2023 13:01:14 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28FFB530D3 for ; Wed, 8 Feb 2023 10:01:04 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id hn2-20020a05600ca38200b003dc5cb96d46so2057962wmb.4 for ; Wed, 08 Feb 2023 10:01:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kfazGtDZ+oWsIm7qBpuVQIZGbKe2YHctFcfaIzg4eRk=; b=AJf/HmZy/DJeFA4L93I2LU6HDwOmEDG6kiy5/LjEvUITXTnJNFgGN510dLgv0yOQ6a 6Nhk57f4+iPOkpwmfOyJ5+hMwB4yq2AxaR2bere2CCN8vxedgjLmTJr+Uyau/LDNL5XU gJMh9240y11YJBruz470E/PbMuouZR2geTc/Pc2wAa0VtlnB2Bt5FQNZXbOrSTNbBmbL jQfkf6wSku71wz/6DdnaDBnXBB1Ej0963UgMOFM2/S08lq0p5n2ZRw3nseseT045vIOK yxthCPkOlrs+OURRVGj54UJ/hpYIPF0glekgjDk6AFWIDqTuzWLJ9+oixMrY/Q42xZJ5 +goQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kfazGtDZ+oWsIm7qBpuVQIZGbKe2YHctFcfaIzg4eRk=; b=N697XFOLHSMv0LjAW6wWEwRNBxk+J9To+woyDFethJO7tHJPwUSyiW8ggnDB4SaECz 9v5Mvawd80Q1+KB3HpL7NqTjXcpIT+qzBWqxQVGCjSl6XQNPyTkKbStu30buP/9dm1DA 4nbkHd4n6gZGbfm6ONCzv98w4xPzQe3CWNM1Ax+G6kjoOesosCnmw2xuyZ89FVdvQdC/ oQPtdAfDcgmbFQrOWVKShAYjewJcT89Kn8Hw2aorfn8kJyyoBzgpYQyNHdrNjdFx/4IP vAyudbGIUSPZGoIz/WTdUQ6uK5D5m3bLl8rktjF0QJVUPJFFaOsAKf73Kf38xbecimOT zDmg== X-Gm-Message-State: AO0yUKXOsVntKfsy9N53LBo2ZlljkJT+sVM9XZxkZlPa3yFgb2cCdrH8 +txV0wCG+4aV0O+TziMQOOVkrg== X-Google-Smtp-Source: AK7set/1bTixNC+cV1xPID2qM+owEopJQcdX/0CltAtE8FXx1nrVoY72RhtAlpazghcrh6DfMnrCTg== X-Received: by 2002:a05:600c:707:b0:3df:ea9a:21c9 with SMTP id i7-20020a05600c070700b003dfea9a21c9mr8135595wmn.27.1675879263589; Wed, 08 Feb 2023 10:01:03 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id k20-20020a05600c169400b003dc54eef495sm2370286wmn.24.2023.02.08.10.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Feb 2023 10:01:03 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Johan Hovold Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v9 10/11] PCI: qcom: Add SM8550 PCIe support Date: Wed, 8 Feb 2023 20:00:19 +0200 Message-Id: <20230208180020.2761766-11-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230208180020.2761766-1-abel.vesa@linaro.org> References: <20230208180020.2761766-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add compatible for both PCIe found on SM8550. Also add the noc_aggr and cnoc_sf_axi clocks needed by the SM8550. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Reviewed-by: Johan Hovold --- The v8 of this patch is: https://lore.kernel.org/all/20230206212619.3218741-11-abel.vesa@linaro.org/ Changes since v8: * added Johan's R-b tag Changes since v7: * Mentioned the noc_aggr clock in the commit message as well, while using the cnoc_sf_axi instead of cnoc_pcie_sf_axi Changes since v6: * none Changes since v5: * none Changes since v4: * added Mani's R-b tag Changes since v3: * renamed cnoc_pcie_sf_axi to cnoc_sf_axi Changes since v2: * none Changes since v1: * changed the subject line prefix for the patch to match the history, like Bjorn Helgaas suggested. * added Konrad's R-b tag drivers/pci/controller/dwc/pcie-qcom.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a232b04af048..6a70c9c6f98d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,10 +182,10 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[14]; int num_clks; struct regulator_bulk_data supplies[2]; - struct reset_control *pci_reset; + struct reset_control *rst; }; struct qcom_pcie_resources_2_9_0 { @@ -1177,9 +1177,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) unsigned int idx; int ret; - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); - if (IS_ERR(res->pci_reset)) - return PTR_ERR(res->pci_reset); + res->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(res->rst)) + return PTR_ERR(res->rst); res->supplies[0].supply = "vdda"; res->supplies[1].supply = "vddpe-3v3"; @@ -1205,9 +1205,11 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "ddrss_sf_tbu"; res->clks[idx++].id = "aggre0"; res->clks[idx++].id = "aggre1"; + res->clks[idx++].id = "noc_aggr"; res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "cnoc_sf_axi"; num_opt_clks = idx - num_clks; res->num_clks = idx; @@ -1237,17 +1239,17 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) if (ret < 0) goto err_disable_regulators; - ret = reset_control_assert(res->pci_reset); - if (ret < 0) { - dev_err(dev, "cannot assert pci reset\n"); + ret = reset_control_assert(res->rst); + if (ret) { + dev_err(dev, "reset assert failed (%d)\n", ret); goto err_disable_clocks; } usleep_range(1000, 1500); - ret = reset_control_deassert(res->pci_reset); - if (ret < 0) { - dev_err(dev, "cannot deassert pci reset\n"); + ret = reset_control_deassert(res->rst); + if (ret) { + dev_err(dev, "reset deassert failed (%d)\n", ret); goto err_disable_clocks; } @@ -1841,6 +1843,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, { } };