From patchwork Fri Feb 3 18:21:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 650221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4898BC6379F for ; Fri, 3 Feb 2023 18:21:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233070AbjBCSV5 (ORCPT ); Fri, 3 Feb 2023 13:21:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233519AbjBCSVy (ORCPT ); Fri, 3 Feb 2023 13:21:54 -0500 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFC54AD32F for ; Fri, 3 Feb 2023 10:21:46 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id be12so6029287edb.4 for ; Fri, 03 Feb 2023 10:21:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rx2A0orpFobg6vCQ93gtQtdPGz7VnlCr3bKNpo9fQjE=; b=PKA9uLnzry9YJ4oA4ae6DUc3j2W9fPt7ebKGwfC9d7qmaQXK+9ItKxCxVnVDTeFENg tLrEXfD+tcReLooUjQxH/hxUHIzRLkvdNp+cRHmZWKuzVIaU6aqgddzacOgucZlUmW8G +lWdq9eRkZwglL+Ho4nv06r7sBTE1s/J6ltDBHg1/lgSZSrp7Y/euzdJiq/y3j2IUZ8t /+dwq7m+HSf6r9nETqFg2LWgc7WhtyJeIPPEpvQ9cwYNZJ/ykBfRllHRjvFK3SN01pjq AXLfJ1oEUXaW7InbVLLqD39EIGadA2TIO7EpwwpQTbb3F06DNkPhcl4YQ7NKRybtFzBL 5QiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rx2A0orpFobg6vCQ93gtQtdPGz7VnlCr3bKNpo9fQjE=; b=QRyFWX0irkxyEM0QhVKpQ4FgLEsuRtzoLtEpO8GI6vcQihPhzogqYCsUwzgf09yJBM KuA508Cb4LM0vhmbOmieDvtV1Adu/gS5RJ+5iwHdi9uW35lVBxPWe+1kb8mshhvnnYiC 0GXHNsFnzIvVg92CPnAf8mlDHC3M8+WgmvJIx8JmVg5ojLrgPseYFDQC1trTZBIl1x1V R2vxmg4iLAaw5ysVkPFUSVkNAAbyqgp3PNhLaqaf+E2Cs3yd8rmpANS07OPQrgte4xZm C2pAMgwExgcH2D6NQKI146f6NWlHimSZpZoBw5aLK2/RuolaUvy05CtTb0HyCC2cEIPL 4Iyg== X-Gm-Message-State: AO0yUKVZe28iBpHhUDbRT16du/kUl2M49KbSbAzAmWgOE10QSsKblNmR 1Ze6M7BYS8y+hMzUbbHFeryw3Q== X-Google-Smtp-Source: AK7set9f0Y6DO+b46vlzwE2VoUdxKvkqJtbHlYbdylchWMvKkpZIjcCyOQApIsHlIuIvgaYM1RWe0Q== X-Received: by 2002:a50:8a96:0:b0:4a2:70cb:c86c with SMTP id j22-20020a508a96000000b004a270cbc86cmr12365491edj.13.1675448504887; Fri, 03 Feb 2023 10:21:44 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w16-20020a05640234d000b0046267f8150csm1487523edc.19.2023.02.03.10.21.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 10:21:44 -0800 (PST) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v3 09/27] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3() Date: Fri, 3 Feb 2023 20:21:14 +0200 Message-Id: <20230203182132.1307834-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230203182132.1307834-1-dmitry.baryshkov@linaro.org> References: <20230203182132.1307834-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no need to pass full dpu_hw_sspp_cfg instance to _dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 9 ++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++-- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 4d3ca8532563..abf499275242 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -419,19 +419,18 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, } static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *sspp, - void *scaler_cfg) + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct dpu_format *format) { u32 idx; - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !scaler3_cfg) return; dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, ctx->cap->sblk->scaler_blk.version, - sspp->layout.format); + format); } static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 8d566ad1877e..5e9b07090a21 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops { /** * setup_scaler - setup scaler - * @ctx: Pointer to pipe context - * @pipe_cfg: Pointer to pipe configuration - * @scaler_cfg: Pointer to scaler configuration + * @scaler3_cfg: Pointer to scaler configuration + * @format: pixel format parameters */ void (*setup_scaler)(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *pipe_cfg, - void *scaler_cfg); + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct dpu_format *format); /** * get_scaler_ver - get scaler h/w version diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 8f1767619d06..4f5c44d78332 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, if (pipe_hw->ops.setup_scaler && pipe->multirect_index != DPU_SSPP_RECT_1) pipe_hw->ops.setup_scaler(pipe_hw, - pipe_cfg, - &scaler3_cfg); + &scaler3_cfg, + fmt); } /**