From patchwork Thu Feb 2 13:25:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 649733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32F5CC64ED6 for ; Thu, 2 Feb 2023 13:25:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232390AbjBBNZb (ORCPT ); Thu, 2 Feb 2023 08:25:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232446AbjBBNZ0 (ORCPT ); Thu, 2 Feb 2023 08:25:26 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9F728F509 for ; Thu, 2 Feb 2023 05:25:23 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id k16so1387099wms.2 for ; Thu, 02 Feb 2023 05:25:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ulnnpkYgMQ4L/Y0J72rRJwuK32aNfc72t69x/YeVogc=; b=rHd4oieIm5lvw6HovpYXcY3J3IXrNtgfRb80RmJuAJdqCRxYeC/kSxBmqyrv3dJKmD A4PCj6CzEi+PERow+nTbnkKEWSMiyIV9jkpK6C899URPhbxl9hEyJe5CSveZewPMFIF/ ZX5kqKIWlD6km3Rrx6pImngZIqQLfJku6fVfXz735C5hiGdGfpKeqMUj3r8s+6/8O2tN ZxwsvYcf4pUHX9wMroec5V73DqOQ8BKigRXicxFZkoMDuaPgM1QieXnXnwtOWoVD4r8A 3fYlWLNguoFo6iOB83KDU3wIZUaI3d32iyKp/boJWO8OLsUfC1ybYPVnr5MLX7+cEANq AGuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ulnnpkYgMQ4L/Y0J72rRJwuK32aNfc72t69x/YeVogc=; b=CF0m5i1gdPr6qxczzEqmMbkHMmINzyDnhNZw21Dmikt9slYH7kTpwneSQSvoDtStbz bRVFUemUTZ91V3Ug9Y33+iYd9RwnTicbi1r63ZUT9P8qW8OYnvmBgrZE2UYlNmixXNtG ikrIdTfMEZyn9iaeodTf1CIprGR5MXIgp9KspcoWvW+MKF0ZV48PCw2h07Tb+K0bLs9N fya0Osr5YuEcrwIYHSjIa5inyrvYI5pmotj5bgt2tvXe8pgDaGT/Qyzj3IX0+QZn+JU9 t+zT5QqFvCAAA3K0iPswbrET5/lV4mYqyUoXbWMQVv9YjxSTapxKbt5CwjSnGbRHqM3t Gx2g== X-Gm-Message-State: AO0yUKUmFLwjax9U9suqC3IFBVQ+tFDo7SUgfWr3g8YMT956aaoI3Dw0 CyNTXWAtUjxxvZFAGoP5j3f8ZQ== X-Google-Smtp-Source: AK7set+ql1RJGksX7KGshDvlnEJZnAemEsMxLnK9r0sJptjwTeMV3DEISbiLJuTXmsrCgLqAXtF/Ug== X-Received: by 2002:a05:600c:a48:b0:3dc:5d34:dbe5 with SMTP id c8-20020a05600c0a4800b003dc5d34dbe5mr6111682wmq.28.1675344323299; Thu, 02 Feb 2023 05:25:23 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id e22-20020a05600c449600b003db06224953sm4690943wmo.41.2023.02.02.05.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 05:25:22 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v4 7/8] arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes Date: Thu, 2 Feb 2023 15:25:10 +0200 Message-Id: <20230202132511.3983095-8-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202132511.3983095-1-abel.vesa@linaro.org> References: <20230202132511.3983095-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add USB host controller and PHY nodes. Signed-off-by: Abel Vesa --- Changes since v3: * none Changes since v2: * none NOTE: This patch has been already merged. It is here only to provide context for the rest of the patchset. There is a change with respect to the clocks, but that will be sent as a separate/individual fix patch. arch/arm64/boot/dts/qcom/sm8550.dtsi | 92 +++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a85d2ae7d155..0262193e2ffe 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include / { @@ -746,7 +747,7 @@ gcc: clock-controller@100000 { <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, - <0>; + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; ipcc: mailbox@408000 { @@ -2060,6 +2061,95 @@ opp-202000000 { }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088e3000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8550-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x3000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB3_PHY_GDSC>; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a6f8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&rpmhcc TCSR_USB3_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a600000 0x0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x40 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8550-mdss"; reg = <0 0x0ae00000 0 0x1000>;