diff mbox series

[v4,7/8] arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes

Message ID 20230202132511.3983095-8-abel.vesa@linaro.org
State Accepted
Commit 7f7e5c1b037fc38dfc4f9530fcdb6fa8bd9fd01c
Headers show
Series sm8550: Add USB HC and PHYs support | expand

Commit Message

Abel Vesa Feb. 2, 2023, 1:25 p.m. UTC
Add USB host controller and PHY nodes.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---

Changes since v3:
 * none

Changes since v2:
 * none

NOTE: This patch has been already merged. It is here only to provide
context for the rest of the patchset. There is a change with respect to
the clocks, but that will be sent as a separate/individual fix patch.

 arch/arm64/boot/dts/qcom/sm8550.dtsi | 92 +++++++++++++++++++++++++++-
 1 file changed, 91 insertions(+), 1 deletion(-)

Comments

Abel Vesa Feb. 7, 2023, 11:03 a.m. UTC | #1
On 23-02-03 11:55:11, Johan Hovold wrote:
> On Thu, Feb 02, 2023 at 03:25:10PM +0200, Abel Vesa wrote:
> > Add USB host controller and PHY nodes.
> > 
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> > 
> > Changes since v3:
> >  * none
> > 
> > Changes since v2:
> >  * none
> > 
> > NOTE: This patch has been already merged. It is here only to provide
> > context for the rest of the patchset. There is a change with respect to
> > the clocks, but that will be sent as a separate/individual fix patch.
> 
> I believe it was because of the 'phy' and 'common' resets, which have
> been switched below.

No, the resets haven't been switched, at least not compared to the
already merged version.

> 
> >  arch/arm64/boot/dts/qcom/sm8550.dtsi | 92 +++++++++++++++++++++++++++-
> >  1 file changed, 91 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index a85d2ae7d155..0262193e2ffe 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -14,6 +14,7 @@
> >  #include <dt-bindings/mailbox/qcom-ipcc.h>
> >  #include <dt-bindings/power/qcom-rpmpd.h>
> >  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> > +#include <dt-bindings/phy/phy-qcom-qmp.h>
> >  #include <dt-bindings/thermal/thermal.h>
> >  
> >  / {
> > @@ -746,7 +747,7 @@ gcc: clock-controller@100000 {
> >  				 <&ufs_mem_phy 0>,
> >  				 <&ufs_mem_phy 1>,
> >  				 <&ufs_mem_phy 2>,
> > -				 <0>;
> > +				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> >  		};
> >  
> >  		ipcc: mailbox@408000 {
> > @@ -2060,6 +2061,95 @@ opp-202000000 {
> >  			};
> >  		};
> >  
> > +		usb_1_hsphy: phy@88e3000 {
> > +			compatible = "qcom,sm8550-snps-eusb2-phy";
> > +			reg = <0x0 0x088e3000 0x0 0x154>;
> > +			#phy-cells = <0>;
> > +
> > +			clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
> > +			clock-names = "ref";
> > +
> > +			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> > +
> > +			status = "disabled";
> > +		};
> > +
> > +		usb_dp_qmpphy: phy@88e8000 {
> > +			compatible = "qcom,sm8550-qmp-usb3-dp-phy";
> > +			reg = <0x0 0x088e8000 0x0 0x3000>;
> > +
> > +			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> > +				 <&rpmhcc RPMH_CXO_CLK>,
> > +				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> > +				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> > +			clock-names = "aux", "ref", "com_aux", "usb3_pipe";
> > +
> > +			power-domains = <&gcc USB3_PHY_GDSC>;
> > +
> > +			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> > +				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
> > +			reset-names = "phy", "common";
> > +
> > +			#clock-cells = <1>;
> > +			#phy-cells = <1>;
> > +
> > +			status = "disabled";
> > +		};
> 
> Johan
Johan Hovold Feb. 7, 2023, 11:16 a.m. UTC | #2
On Tue, Feb 07, 2023 at 01:03:26PM +0200, Abel Vesa wrote:
> On 23-02-03 11:55:11, Johan Hovold wrote:
> > On Thu, Feb 02, 2023 at 03:25:10PM +0200, Abel Vesa wrote:
> > > Add USB host controller and PHY nodes.
> > > 
> > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > > ---
> > > 
> > > Changes since v3:
> > >  * none
> > > 
> > > Changes since v2:
> > >  * none
> > > 
> > > NOTE: This patch has been already merged. It is here only to provide
> > > context for the rest of the patchset. There is a change with respect to
> > > the clocks, but that will be sent as a separate/individual fix patch.
> > 
> > I believe it was because of the 'phy' and 'common' resets, which have
> > been switched below.
> 
> No, the resets haven't been switched, at least not compared to the
> already merged version.

The resets were wrong in the merged version just as they are below. I've
already sent a fix here:

	https://lore.kernel.org/lkml/20230123101607.2413-1-johan+linaro@kernel.org/
 
> > > +		usb_dp_qmpphy: phy@88e8000 {
> > > +			compatible = "qcom,sm8550-qmp-usb3-dp-phy";
> > > +			reg = <0x0 0x088e8000 0x0 0x3000>;
> > > +
> > > +			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> > > +				 <&rpmhcc RPMH_CXO_CLK>,
> > > +				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> > > +				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> > > +			clock-names = "aux", "ref", "com_aux", "usb3_pipe";
> > > +
> > > +			power-domains = <&gcc USB3_PHY_GDSC>;
> > > +
> > > +			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> > > +				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
> > > +			reset-names = "phy", "common";

Johan
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index a85d2ae7d155..0262193e2ffe 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -14,6 +14,7 @@ 
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -746,7 +747,7 @@  gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 0>,
 				 <&ufs_mem_phy 1>,
 				 <&ufs_mem_phy 2>,
-				 <0>;
+				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 		};
 
 		ipcc: mailbox@408000 {
@@ -2060,6 +2061,95 @@  opp-202000000 {
 			};
 		};
 
+		usb_1_hsphy: phy@88e3000 {
+			compatible = "qcom,sm8550-snps-eusb2-phy";
+			reg = <0x0 0x088e3000 0x0 0x154>;
+			#phy-cells = <0>;
+
+			clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+			status = "disabled";
+		};
+
+		usb_dp_qmpphy: phy@88e8000 {
+			compatible = "qcom,sm8550-qmp-usb3-dp-phy";
+			reg = <0x0 0x088e8000 0x0 0x3000>;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux", "ref", "com_aux", "usb3_pipe";
+
+			power-domains = <&gcc USB3_PHY_GDSC>;
+
+			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <1>;
+			#phy-cells = <1>;
+
+			status = "disabled";
+		};
+
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a6f8800 0x0 0x400>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+				 <&rpmhcc TCSR_USB3_CLKREF_EN>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 15 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 14 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "hs_phy_irq",
+					  "ss_phy_irq",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
+
+			power-domains = <&gcc USB30_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+			status = "disabled";
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a600000 0x0 0xcd00>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x40 0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,usb3_lpm_capable;
+				phys = <&usb_1_hsphy>,
+				       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
 		mdss: display-subsystem@ae00000 {
 			compatible = "qcom,sm8550-mdss";
 			reg = <0 0x0ae00000 0 0x1000>;