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[1/2] dt-bindings: interconnect: Add Qualcomm CCI dt-bindings

Message ID 20230201080227.473547-1-jun.nie@linaro.org
State New
Headers show
Series [1/2] dt-bindings: interconnect: Add Qualcomm CCI dt-bindings | expand

Commit Message

Jun Nie Feb. 1, 2023, 8:02 a.m. UTC 
Add devicetree binding of Qualcomm CCI on MSM8939.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
 .../bindings/interconnect/qcom,cci.yaml       | 81 +++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,cci.yaml
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Patch

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,cci.yaml b/Documentation/devicetree/bindings/interconnect/qcom,cci.yaml
new file mode 100644
index 000000000000..100c440ba220
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,cci.yaml
@@ -0,0 +1,81 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Cache Coherent Interconnect (CCI) frequency and voltage scaling
+
+maintainers:
+  - Jun Nie <jun.nie@linaro.org>
+
+description: |
+  Qualcomm Cache Coherent Interconnect (CCI) is a hardware engine used by
+  MSM8939. The driver is to scale its frequency and adjust the voltage in
+  hardware accordingly. The voltage provider is modeled as power domain on
+  MSM8939, so power domain dts node is required.
+
+properties:
+  compatible:
+    enum:
+      - qcom,msm8939-cci
+
+  clocks:
+    maxItems: 1
+
+  operating-points-v2: true
+  opp-table:
+    type: object
+
+required:
+  - compatible
+  - clocks
+  - operating-points-v2
+  - nvmem-cells
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    cci: cci {
+        compatible = "qcom,msm8939-cci";
+	clocks = <&apcs2>;
+	operating-points-v2 = <&cci_opp_table>;
+	power-domains = <&cpr>;
+	nvmem-cells = <&cpr_efuse_speedbin_pvs>;
+    };
+
+    cci_opp_table: cci-opp-table {
+	compatible = "operating-points-v2";
+
+	cci_opp1: opp-200000000 {
+	       opp-hz = /bits/ 64 <200000000>;
+	       opp-supported-hw = <0x3f>;
+	       required-opps = <&cpr_opp3>;
+	};
+
+	cci_opp2: opp-297600000 {
+	       opp-hz = /bits/ 64 <297600000>;
+	       opp-supported-hw = <0x3f>;
+	       required-opps = <&cpr_opp12>;
+	};
+
+	cci_opp3: opp-400000000 {
+	       opp-hz = /bits/ 64 <400000000>;
+	       opp-supported-hw = <0x1>;
+	       required-opps = <&cpr_opp14>;
+	};
+
+	cci_opp4: opp-400000000 {
+	       opp-hz = /bits/ 64 <400000000>;
+	       opp-supported-hw = <0x3e>;
+	       required-opps = <&cpr_opp15>;
+	};
+
+	cci_opp5: opp-595200000 {
+	       opp-hz = /bits/ 64 <595200000>;
+	       opp-supported-hw = <0x3f>;
+	       required-opps = <&cpr_opp17>;
+	};
+    };