From patchwork Thu Jan 26 14:40:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 647633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A066C61DA2 for ; Thu, 26 Jan 2023 14:40:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231863AbjAZOkt (ORCPT ); Thu, 26 Jan 2023 09:40:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229491AbjAZOks (ORCPT ); Thu, 26 Jan 2023 09:40:48 -0500 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 521BD76A6 for ; Thu, 26 Jan 2023 06:40:46 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id v6so5610037ejg.6 for ; Thu, 26 Jan 2023 06:40:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IrFPxpcXauUCjSJ1xRyDF+r/rVJ2enA59bYfUgUOYx4=; b=c57OUNlBNlPoR81q5Kb6sg4ldd4EFJxzQZrQs41VRo35h+2vGnFoC6Mclal18r4HzM hwwnA2lKx4/r/WaMGJA33e6DNtr6+EF6mRQUJQFCvuguEaqeSCgimepGRmU21OY8aHls uaOydfzy9+IKVVoSUq41GlMifkUSnFiy2wdbe2YgQPbvAchTrtlUPN73yaniHfSPS1fL aGK4b5deIOqYdSZBR4oc+jo7x/DFC3cjI3b1lkLBzDDlVopfZxfbACV9DcQlxPttJXVn gBkayUKUSmdM6YYNPGEdLwuiOHdWbg3rbU7wcKG9DnTOuY1O9gXBtmCFuAUsa5dX94TD nZoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IrFPxpcXauUCjSJ1xRyDF+r/rVJ2enA59bYfUgUOYx4=; b=mJjeyVqcitAJIiLxiA0mvRjJraR0Uy8+YvItJCeEZmpLS4GNgQIlWGzhHmiMifGEYk 0yJ+RpIA4QsMApZxmA9M2PPCZ6w+MjQwFqLKU3RI3RHdXfUvjXXEgTRlq0G+DJ9TFkVs WA+8cm21QcYtFCsGk+bdmUHqtoMsXBk26Um6kMsod7hrmDxfvMoOxv9aQCuiARKMA8DH dW4mWvcB44Hl/e3exiItBtptAniPTAhhEy1IKK9jZ/SteTJVsJnCSRZQElGCcG3wys9U NZe4irYplJtpbUC+3TKPSIQZ7Oum0TuLXAZprP9RL6JOtZV0UNgAoqwbXmIKjmRQZlpj aSBw== X-Gm-Message-State: AFqh2kor5YwHQI8EY10NbMHnoD3pJVkFiuZ1PG37TwdhfXFJk43fhbdA waZML6wqzIFpH+DxIblvRrPbkEBOYkrbz3f4 X-Google-Smtp-Source: AMrXdXuG1NCHlDPWwadVs+e4B6jOmjWWgqY2QmZDIehqUBVhKvLAs1qnxMSM+s5AMIukIWSjRr+SZA== X-Received: by 2002:a17:906:2402:b0:874:e17e:2526 with SMTP id z2-20020a170906240200b00874e17e2526mr32612934eja.72.1674744044643; Thu, 26 Jan 2023 06:40:44 -0800 (PST) Received: from localhost.localdomain (abyk108.neoplus.adsl.tpnet.pl. [83.9.30.108]) by smtp.gmail.com with ESMTPSA id s19-20020a1709060c1300b008699bacc03csm697547ejf.14.2023.01.26.06.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 06:40:44 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: clock: Add Qcom SM6125 GPUCC Date: Thu, 26 Jan 2023 15:40:28 +0100 Message-Id: <20230126144033.216206-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126144033.216206-1-konrad.dybcio@linaro.org> References: <20230126144033.216206-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6125 SoCs. Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,sm6125-gpucc.yaml | 64 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6125-gpucc.h | 31 +++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6125-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml new file mode 100644 index 000000000000..374a1844a159 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6125 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6125-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6125-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6125-gpucc.h b/include/dt-bindings/clock/qcom,sm6125-gpucc.h new file mode 100644 index 000000000000..ce5bd920f2c4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6125-gpucc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H + +/* Clocks */ +#define GPU_CC_PLL0_OUT_AUX2 0 +#define GPU_CC_PLL1_OUT_AUX2 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GFX3D_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_SLEEP_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_AHB_CLK 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif