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([178.197.216.144]) by smtp.gmail.com with ESMTPSA id l30-20020a05600c1d1e00b003c6b70a4d69sm10974120wms.42.2023.01.23.00.43.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 00:43:12 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [RFT PATCH v3 5/6] arm64: dts: qcom: sdm845-audio-wcd9340: commonize pinctrl Date: Mon, 23 Jan 2023 09:42:59 +0100 Message-Id: <20230123084300.22353-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230123084300.22353-1-krzysztof.kozlowski@linaro.org> References: <20230123084300.22353-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Pin configuration fow WCD9340 is the same in all users, so move it to common file to reduce the code duplication (which still allows further customizations per board). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes since v2: 1. None Changes since v1: 1. Add Rb tag. 2. Split from previous patchset. --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 11 ----------- arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi | 15 +++++++++++++++ .../dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 11 ----------- .../arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 10 ---------- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 11 ----------- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 11 ----------- 6 files changed, 15 insertions(+), 54 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 118cc50ce49b..c7a12257ac75 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -973,15 +973,6 @@ sdc2_card_det_n: sd-card-det-n-state { function = "gpio"; bias-pull-up; }; - - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart3 { @@ -1087,8 +1078,6 @@ &venus { }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi b/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi index 5bcce7d0d709..33718cb95c83 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi @@ -32,6 +32,10 @@ wcd9340: codec@1,0 { #clock-cells = <0>; clock-frequency = <9600000>; clock-output-names = "mclk"; + + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + qcom,micbias1-microvolt = <1800000>; qcom,micbias2-microvolt = <1800000>; qcom,micbias3-microvolt = <1800000>; @@ -67,3 +71,14 @@ swm: swm@c85 { }; }; }; + +&tlmm { + wcd_intr_default: wcd-intr-default-state { + pins = "gpio54"; + function = "gpio"; + + input-enable; + bias-pull-down; + drive-strength = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index a472c716f966..57f1c5925cb0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -466,15 +466,6 @@ sdc2_card_det_n: sd-card-det-n-state { function = "gpio"; bias-pull-up; }; - - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart6 { @@ -543,8 +534,6 @@ &venus { }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index ea2a1a9fb3ff..468867363f18 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -616,14 +616,6 @@ sde_dsi_suspend: sde-dsi-suspend-state { drive-strength = <2>; bias-pull-down; }; - - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart6 { @@ -700,8 +692,6 @@ &venus { }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 6d253fbe0267..a461cb7f6bd2 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -628,15 +628,6 @@ i2c11_hid_active: i2c11-hid-active-state { drive-strength = <2>; }; - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; - lid_pin_active: lid-pin-state { pins = "gpio124"; function = "gpio"; @@ -747,8 +738,6 @@ &venus { }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 6758b0698acc..d4ae2788bada 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -552,15 +552,6 @@ pen_rst_l: pen-rst-l-state { */ output-high; }; - - wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart6 { @@ -656,8 +647,6 @@ &venus { }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;