From patchwork Wed Jan 18 00:38:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 643800 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77537C38159 for ; Wed, 18 Jan 2023 00:51:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229706AbjARAv3 (ORCPT ); Tue, 17 Jan 2023 19:51:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230002AbjARAuK (ORCPT ); Tue, 17 Jan 2023 19:50:10 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85D7D48589 for ; Tue, 17 Jan 2023 16:38:48 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id iv8-20020a05600c548800b003db04a0a46bso587708wmb.0 for ; Tue, 17 Jan 2023 16:38:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cUb/S2D/vEg5DXQcpUFp2Jq273wdmh34OP7UkZOQF4I=; b=R2mEcqok6JYrd6hI+uMJg2GlORMxPbzmaRt0kLhbLTe1VfpahOcBvzhPysf+MvOpW4 mH471MTdxiVaVO2fGRe4Pa23QVezlnQpifp4fk6vugs20pbF7BJ0szLJ0lw6MESQwyLB xFbfxB9F0zvifo2yUI99hfZJtzyfeM3pTwFoXsW1GAV6ndSfz83LpPMgyVJJS5tZfuth YJQ/6hklo3miyMprK5hxs8Af9ek7y7tvgS1LVnYCgZhq9ObaMtWCZGnQF1rWOckoFPeV YwbweSqDAVj190D+ie2oGA4xsSFb8p9q3DiBxFIcPEpuy1WaIVu/CW4iR/dPtuUQa8Ai yCPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cUb/S2D/vEg5DXQcpUFp2Jq273wdmh34OP7UkZOQF4I=; b=1Yvq1CDwbw95BMZ9mEA761xj8969nhwJCq5xel2xC/+DsXegyQAzuZprVbPB4Rm55H 3neF+WyMSplGfX2uhKjE7iispntMqXbTXUcCE0DmOBsULbArBlDRAI3ATXoPEWGw42u6 cSjbGCNXI98jg5Lh3UJe7LSHpq2qkCc41HCnjVMiuPc04akpr0ydbKPlbJVr/ntWIu3c 3BrL4RncIcPIgQsfRNX0FZCQfwPi6ZDPVU38wvLKF9O1T0ztu3pLrn5vk6k71pPjf/0V cut7BlI44cGp0D2A6yJOVGb29oFFjtjdrCzX9ibxhCAtArXLOAqGSR2f1AVRuCrKceDD sCHA== X-Gm-Message-State: AFqh2kr7UTDX7cgASfiwNSjz/O3z3Z17pJ3B8dvtjDnwI3B62fk0qnyM YcgaUZPffQCkmIOjS96B5dTLjX9EJZR8Lsn+ X-Google-Smtp-Source: AMrXdXuOy9ruiudQyEeh1GFJ0qSSteo2YtC/fdafCMAhj+OHLtvU/u7CunUrNz87zK0JYvnds/J34A== X-Received: by 2002:a05:600c:510d:b0:3da:f6ae:faa9 with SMTP id o13-20020a05600c510d00b003daf6aefaa9mr10134566wms.29.1674002327050; Tue, 17 Jan 2023 16:38:47 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id m9-20020a7bca49000000b003d98f92692fsm365199wml.17.2023.01.17.16.38.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 16:38:46 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , "vkoul@kernel.org" , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Johan Hovold Subject: [PATCH v2 3/7] phy: qcom-qmp: pcs-pcie: Add v6 register offsets Date: Wed, 18 Jan 2023 02:38:30 +0200 Message-Id: <20230118003834.2330028-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230118003834.2330028-1-abel.vesa@linaro.org> References: <20230118003834.2330028-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 21727e90fad1..d4ca38f31e3f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -29,6 +29,7 @@ #include "phy-qcom-qmp-pcs-pcie-v4_20.h" #include "phy-qcom-qmp-pcs-pcie-v5.h" #include "phy-qcom-qmp-pcs-pcie-v5_20.h" +#include "phy-qcom-qmp-pcs-pcie-v6.h" #include "phy-qcom-qmp-pcie-qhp.h" /* QPHY_SW_RESET bit */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h new file mode 100644 index 000000000000..91e70002eb47 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_H_ + +/* Only for QMP V6 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 + +#endif