From patchwork Tue Jan 17 22:41:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 643499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55571C00A5A for ; Tue, 17 Jan 2023 23:08:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229890AbjAQXH7 (ORCPT ); Tue, 17 Jan 2023 18:07:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229819AbjAQXHW (ORCPT ); Tue, 17 Jan 2023 18:07:22 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A500746178 for ; Tue, 17 Jan 2023 14:42:05 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id bk16so32146843wrb.11 for ; Tue, 17 Jan 2023 14:42:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=opi8RvSZyWqP5CZd/RMpwXuivdX51quIupzhmRNYojE=; b=IA6dGsvmzLiwhZXdTikAJ8mTUC6YA3P65k3telk2m5btZwxZv20Ly1KZLgxHJFDf1x 4E4CKBX64PCIolajLA8rDzE5DJWgH8+ms+VvWCMXTcyD0H3ykdSWcOky3uA/B472pUi/ YF+QHgFEP7WCiDHZV3ogLiMuRq7HRR7QJ+BZiFIGdbjhY7i3gb3nvYKcv6Yse6T2BLZ4 bZc40DKPV71H1ruKA9q+npIb5va9yKAG2ESrdk7Z51nlUv+Ylz7STPIjTlyDUNQbgV7w HmSZDsyQGOljPFlQuWMbpPrsZE6mJtw8nqX9MJkOYo2Uw8GzM4ZU9yNFbtov/DA2aaFm 2Gtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=opi8RvSZyWqP5CZd/RMpwXuivdX51quIupzhmRNYojE=; b=059leVu/v0zuWiLrWC8PFFNDaGIkirtauUFNkVsX/QjJ11SVBJd2hqia911UZrshdd zunutDnLQCG+wH7o8DO+8ntBhQPZU8uJwvcTZyhdyRod55RRhf4AumLQnX0Vhq7oTeUt sfYmnNcfOrvoqa1AxxqmDl/RbjDdJy4ORm3r04+2ZZtVKAFqkuUDOiPqBiRzW4DRE26q oslgzIBBOIcC98G29QR6zLQCRHz8g6sZrEiRuwmAgX0mJk2eyFVy4Poorl+agkAkQZUF LqsTL6YUU7Udo9dcb2XMhnupcf/blD7xx33rf06mrFdqjUCgSzOO/mdDZNQAkLcggyrf U+Wg== X-Gm-Message-State: AFqh2kq0EsceEb6kTcCJD5tQhfwKxnCKSxlwQ8W4YBnzc4qGEWgKZPpo CYpS4ItesztvqDwQU3odCSqfuA== X-Google-Smtp-Source: AMrXdXt/YsYerSWEk+vpszivx09XXHrKpmRGoXBsQnkBdiYPUPJ6pm71BrMMCP2s9UYlN7gJdLR+JQ== X-Received: by 2002:a5d:6a46:0:b0:2bd:c856:6de0 with SMTP id t6-20020a5d6a46000000b002bdc8566de0mr4402073wrw.21.1673995320923; Tue, 17 Jan 2023 14:42:00 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id m1-20020a5d6241000000b002bbdaf21744sm27024916wrv.113.2023.01.17.14.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 14:42:00 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , "vkoul@kernel.org" , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Johan Hovold , Dmitry Baryshkov Subject: [PATCH v5 5/6] phy: qcom-qmp: pcs-ufs: Add v6 register offsets Date: Wed, 18 Jan 2023 00:41:47 +0200 Message-Id: <20230117224148.1914627-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117224148.1914627-1-abel.vesa@linaro.org> References: <20230117224148.1914627-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated header file. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 31 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 1 + 2 files changed, 32 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h new file mode 100644 index 000000000000..c23d5e41e25b --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_ +#define QCOM_PHY_QMP_PCS_UFS_V6_H_ + +/* Only for QMP V6 PHY - UFS PCS registers */ +#define QPHY_V6_PCS_UFS_PHY_START 0x000 +#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V6_PCS_UFS_SW_RESET 0x008 +#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c +#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 +#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c +#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 +#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 +#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 +#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc +#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158 +#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c +#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184 +#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c +#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178 +#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174 +#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8 +#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4 +#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index a5cdd58c5b4d..f142235432e1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -26,6 +26,7 @@ #include "phy-qcom-qmp-pcs-ufs-v3.h" #include "phy-qcom-qmp-pcs-ufs-v4.h" #include "phy-qcom-qmp-pcs-ufs-v5.h" +#include "phy-qcom-qmp-pcs-ufs-v6.h" #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"