From patchwork Tue Jan 17 22:41:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 643808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 890B0C00A5A for ; Tue, 17 Jan 2023 23:07:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230045AbjAQXHs (ORCPT ); Tue, 17 Jan 2023 18:07:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229734AbjAQXHM (ORCPT ); Tue, 17 Jan 2023 18:07:12 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF4D83E60B for ; Tue, 17 Jan 2023 14:41:58 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id h16so32157666wrz.12 for ; Tue, 17 Jan 2023 14:41:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4QrCB0vKJwHvjsPAbNQg49wm7woRPfh3dy/MvNe12rU=; b=h1G83ntrbdcYzGO5/rZzyGlrqnm8zy69SOjuAnE/uDPW1ZpgvHm/1o7z1y/eELGR8e wtjpoaSKijqW6l40eMI2u+t9cX1iEKckZ7eEAPIg+FcJOJGqlqD0ejyiwtsWR2ly4LQi aYL1qmoAp+8AMOxWGN2tZ6bN7uNKvwfvMw3kOAvhtVpC4rhnTFwJd5Gf3rpq1UK1xFBn 18XL3W57ftIpUfx6umzTaVB6I4sNxq5Y/joOTBSm+Y2/aXtfC/3MlePsV7Ipyyvm1owK Qs2Zk2P4QI/uFUZr0dpeb2fBS3yhKwJv0uUe5WwUCgre2il/kF3hOvpMm4xYxnCkG8vF HDBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4QrCB0vKJwHvjsPAbNQg49wm7woRPfh3dy/MvNe12rU=; b=EdXvHjuQASufAG4HAhRRyw50qfzegIyBDGqgs2UNFRNXxUUHcVbgpjm3RCMLlN5aYu vT+5UzV09eBLtNTF1IuXuX5xLGWWyldDAdlE9KdeAzoIn/ANE9OME0/LTP94QhcTdd2l l8U8zfDm+VRRaiivCgXoMB13MTyYdr+BKzW63pGmG/A2SD2i43007/Y32h1De6HNk3l3 mbcQZiMddRyLGmoa4NDxIno/UbfUMvip+amjrrocLJo4wTVKthRpu3vi5KrhS49kL62T uCZT27YObfMyfNY64ej48/+6uiUxlULUasgIzSNX4tnGqHeGvkkiWBgiAV5lKKJOsanc RmcA== X-Gm-Message-State: AFqh2krPbnk4+n1bz2gqMJIxBZi+jjkF2cIu1MBUI/7WOybVqFnbvNPl rHAM3105GOJ1lboJ3x3n7mpPbQ== X-Google-Smtp-Source: AMrXdXsnkpOeQXMUPrj/7lrqpPEwgz2kOSjEJsl4LlFRFFj8xA8Y08nlbubt//kVovwBymK5aoV7gA== X-Received: by 2002:adf:cf02:0:b0:294:381e:1c7d with SMTP id o2-20020adfcf02000000b00294381e1c7dmr3999604wrj.8.1673995318397; Tue, 17 Jan 2023 14:41:58 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id m1-20020a5d6241000000b002bbdaf21744sm27024916wrv.113.2023.01.17.14.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 14:41:57 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , "vkoul@kernel.org" , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Johan Hovold , Dmitry Baryshkov Subject: [PATCH v5 3/6] phy: qcom-qmp: qserdes-txrx: Add v6 register offsets Date: Wed, 18 Jan 2023 00:41:45 +0200 Message-Id: <20230117224148.1914627-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117224148.1914627-1-abel.vesa@linaro.org> References: <20230117224148.1914627-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX offsets in a dedicated header file. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- .../qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 77 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 2 files changed, 78 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h new file mode 100644 index 000000000000..a69233e68f9a --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ + +#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08 +#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c +#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20 +#define QSERDES_V6_TX_TX_BAND 0x24 +#define QSERDES_V6_TX_INTERFACE_SELECT 0x2c +#define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34 +#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38 +#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c +#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40 +#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 +#define QSERDES_V6_TX_BIST_PATTERN7 0x7c +#define QSERDES_V6_TX_LANE_MODE_1 0x84 +#define QSERDES_V6_TX_LANE_MODE_3 0x8c +#define QSERDES_V6_TX_LANE_MODE_4 0x90 +#define QSERDES_V6_TX_LANE_MODE_5 0x94 +#define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4 +#define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0 +#define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4 +#define QSERDES_V6_TX_VMODE_CTRL1 0xc8 +#define QSERDES_V6_TX_PI_QEC_CTRL 0xe4 + +#define QSERDES_V6_RX_UCDR_FO_GAIN 0x08 +#define QSERDES_V6_RX_UCDR_SO_GAIN 0x14 +#define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30 +#define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34 +#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c +#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 +#define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44 +#define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c +#define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50 +#define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54 +#define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58 +#define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60 +#define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc +#define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4 +#define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8 +#define QSERDES_V6_RX_GM_CAL 0xdc +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 +#define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8 +#define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc +#define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V6_RX_SIDGET_ENABLES 0x118 +#define QSERDES_V6_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V6_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V6_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0 +#define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V6_RX_DCC_CTRL1 0x1a8 +#define QSERDES_V6_RX_VTH_CODE 0x1b0 +#define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4 +#define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index d1275d20a3a3..a63a691b8372 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -22,6 +22,7 @@ #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h" #include "phy-qcom-qmp-qserdes-com-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-v6.h" #include "phy-qcom-qmp-qserdes-pll.h"