From patchwork Thu Dec 29 19:18:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 637578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A858EC3DA79 for ; Thu, 29 Dec 2022 19:19:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233746AbiL2TT0 (ORCPT ); Thu, 29 Dec 2022 14:19:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233970AbiL2TTW (ORCPT ); Thu, 29 Dec 2022 14:19:22 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C39AE8FD4 for ; Thu, 29 Dec 2022 11:19:21 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id 1so28744741lfz.4 for ; Thu, 29 Dec 2022 11:19:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w7+ye+NFJZe0KDTdmSEjWd232bLjzOA6QxoZpECE5vE=; b=uwojrxweP+zXINoLEh8Vz8zqaYKnHHNTILI0AMsxOKjH2mI1g7xvfTH/iZaVa5oMVp 3WlyQu0bcgwMaR7+sekPUCDJbD+lhBSq81DcUGsVL6RWS8H/wtJDpbQL9whnNSGlJhIt ruxf0Pm5DsK1Bp2FsNDECkGIb29hZyVRaOFsKzaaUX32mhaRyaB92eKbhZ7QBova7hL1 /NnriLxEr2vq+xK3WUetih9O4nj79tzyEcpggtzD4+CPVbxruXkG146GPU8dxFNBGWa6 IJv7XK4AP8Yt4jA3/3krVpIyE975Smedha69Kltz3qpWai5L4npgrO2M0mQOG7xz9EoI rKmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w7+ye+NFJZe0KDTdmSEjWd232bLjzOA6QxoZpECE5vE=; b=jgxGWdnOIiOLmO4W6wNgQ0i2M6dvVvcnw+hTsN2wYd15WA1AQJsPNQB4OI+LY3o2kO L0JwkcTNPZohoeTsanXuPwlgX10aushiqXE08cJmViY65BbvPYm1D5v5dWxmQwxz9jQR gs30t9g3JxUGfjhsSi1hP+CYnI67onsyVulp0h5Hj0OxuufIFF5YkI7L2A61hG+FchuQ qRx+zkQp8LgRFXc4gTooVlleOkKG3c17LbfAA/WcTb1KQNXMzscUPTw+7Z95zWu17G8U JAzUJ2VEFTfYBlNPHfDYhYX3ypDG/y+bWhC/AHeDWSlMYonvhcSnB/dQfdKTySadmX2i fMqA== X-Gm-Message-State: AFqh2kpNxcFPGYQOkhDlLQq0E+Kb160oU4WN0ISlFMYbfN3o5KP/e/xy m+iqNBeIdX4+Osg14DjLqmNREw== X-Google-Smtp-Source: AMrXdXuJjq5PMyTu9iqoFWihoyYgYyZFAkcj6zfEKVn5d4rAK9OofrKrfAjiW7Q7Rtw9xS9wHTIWdg== X-Received: by 2002:ac2:5f7b:0:b0:4cb:1dc5:deb1 with SMTP id c27-20020ac25f7b000000b004cb1dc5deb1mr1156029lfc.41.1672341561397; Thu, 29 Dec 2022 11:19:21 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t13-20020ac24c0d000000b004cb10c151fasm1162295lfq.88.2022.12.29.11.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 11:19:20 -0800 (PST) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 24/27] drm/msm/dpu: rework plane CSC setting Date: Thu, 29 Dec 2022 21:18:53 +0200 Message-Id: <20221229191856.3508092-25-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221229191856.3508092-1-dmitry.baryshkov@linaro.org> References: <20221229191856.3508092-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework the code flushing CSC settings for the plane. Separate out the pipe and pipe_cfg as a preparation for r_pipe support. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 45 +++++++++++++---------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index c20e0d9fe0ca..fa59ae007de1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -576,29 +576,18 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, }; -static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt) +static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, const struct dpu_format *fmt) { - struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state); const struct dpu_csc_cfg *csc_ptr; - if (!pdpu) { - DPU_ERROR("invalid plane\n"); - return NULL; - } - if (!DPU_FORMAT_IS_YUV(fmt)) return NULL; - if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe.sspp->cap->features) + if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) csc_ptr = &dpu_csc10_YUV2RGB_601L; else csc_ptr = &dpu_csc_YUV2RGB_601L; - DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", - csc_ptr->csc_mv[0], - csc_ptr->csc_mv[1], - csc_ptr->csc_mv[2]); - return csc_ptr; } @@ -1046,6 +1035,27 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return 0; } +static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) +{ + const struct dpu_format *format = to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb)); + const struct dpu_csc_cfg *csc_ptr; + + if (!pipe->sspp || !pipe->sspp->ops.setup_csc) + return; + + csc_ptr = _dpu_plane_get_csc(pipe, format); + if (!csc_ptr) + return; + + DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", + csc_ptr->csc_mv[0], + csc_ptr->csc_mv[1], + csc_ptr->csc_mv[2]); + + pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); + +} + void dpu_plane_flush(struct drm_plane *plane) { struct dpu_plane *pdpu; @@ -1069,13 +1079,8 @@ void dpu_plane_flush(struct drm_plane *plane) else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); - else if (pstate->pipe.sspp && pstate->pipe.sspp->ops.setup_csc) { - const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb)); - const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt); - - if (csc_ptr) - pstate->pipe.sspp->ops.setup_csc(pstate->pipe.sspp, csc_ptr); - } + else + dpu_plane_flush_csc(pdpu, &pstate->pipe); /* flag h/w flush complete */ if (plane->state)