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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id a12-20020a2e860c000000b0027f770526ebsm1165388lji.75.2022.12.25.19.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 19:11:00 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format Date: Mon, 26 Dec 2022 05:10:57 +0200 Message-Id: <20221226031059.2563165-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226031059.2563165-1-dmitry.baryshkov@linaro.org> References: <20221226031059.2563165-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format from the text description. Signed-off-by: Dmitry Baryshkov --- .../bindings/phy/qcom,pcie2-phy.yaml | 87 +++++++++++++++++++ .../bindings/phy/qcom-pcie2-phy.txt | 42 --------- 2 files changed, 87 insertions(+), 42 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml new file mode 100644 index 000000000000..672035199c19 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCIe2 PHY controller + +maintainers: + - Vinod Koul + +description: + The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm + platforms. + +properties: + compatible: + items: + - const: qcom,qcs404-pcie2-phy + - const: qcom,pcie2-phy + + reg: + items: + - description: PHY register set + + clocks: + items: + - description: a clock-specifier pair for the "pipe" clock + + clock-output-names: + maxItems: 1 + + "#clock-cells": + const: 0 + + "#phy-cells": + const: 0 + + vdda-vp-supply: + description: low voltage regulator + + vdda-vph-supply: + description: high voltage regulator + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: pipe + +required: + - compatible + - reg + - clocks + - clock-output-names + - "#clock-cells" + - "#phy-cells" + - vdda-vp-supply + - vdda-vph-supply + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; +... diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt deleted file mode 100644 index 30064253f290..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt +++ /dev/null @@ -1,42 +0,0 @@ -Qualcomm PCIe2 PHY controller -============================= - -The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm -platforms. - -Required properties: - - compatible: compatible list, should be: - "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" - - - reg: offset and length of the PHY register set. - - #phy-cells: must be 0. - - - clocks: a clock-specifier pair for the "pipe" clock - - - vdda-vp-supply: phandle to low voltage regulator - - vdda-vph-supply: phandle to high voltage regulator - - - resets: reset-specifier pairs for the "phy" and "pipe" resets - - reset-names: list of resets, should contain: - "phy" and "pipe" - - - clock-output-names: name of the outgoing clock signal from the PHY PLL - - #clock-cells: must be 0 - -Example: - phy@7786000 { - compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; - reg = <0x07786000 0xb8>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc GCC_PCIE_0_PIPE_ARES>; - reset-names = "phy", "pipe"; - - vdda-vp-supply = <&vreg_l3_1p05>; - vdda-vph-supply = <&vreg_l5_1p8>; - - clock-output-names = "pcie_0_pipe_clk"; - #clock-cells = <0>; - #phy-cells = <0>; - };