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[4/5] arm64: dts: qcom: sm8450: re-order GCC clocks

Message ID 20221224154255.43499-4-krzysztof.kozlowski@linaro.org
State Accepted
Commit 539a9923683c79e6925dd69a2e2534ec197361c7
Headers show
Series [1/5] arm64: dts: qcom: msm8996: align bus node names with DT schema | expand

Commit Message

Krzysztof Kozlowski Dec. 24, 2022, 3:42 p.m. UTC
Bindings expect GCC clocks in other order:

  sm8450-hdk.dtb: clock-controller@100000: clock-names:1: 'sleep_clk' was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index e1df3dad70fb..bb84bf3899b5 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -731,13 +731,13 @@  gcc: clock-controller@100000 {
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>,
 				 <&pcie0_lane>,
-				 <&pcie1_lane>,
-				 <&sleep_clk>;
+				 <&pcie1_lane>;
 			clock-names = "bi_tcxo",
+				      "sleep_clk",
 				      "pcie_0_pipe_clk",
-				      "pcie_1_pipe_clk",
-				      "sleep_clk";
+				      "pcie_1_pipe_clk";
 		};
 
 		gpi_dma2: dma-controller@800000 {