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[71.184.142.128]) by smtp.gmail.com with ESMTPSA id w7-20020ac843c7000000b003a8163c1c96sm6344207qtn.14.2022.12.19.11.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 11:12:04 -0800 (PST) From: Eric Chanudet To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Halaney , Brian Masney , Eric Chanudet Subject: [PATCH v4 2/4] arm64: dts: qcom: sa8450p-pmics: add rtc node Date: Mon, 19 Dec 2022 14:09:59 -0500 Message-Id: <20221219191000.2570545-3-echanude@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221219191000.2570545-1-echanude@redhat.com> References: <20221219191000.2570545-1-echanude@redhat.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the rtc block on the first pmic to enable the rtc for sa8540p-ride. Signed-off-by: Eric Chanudet Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi index 34fc72896761..c9b8da43b237 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi @@ -13,6 +13,14 @@ pm8450a: pmic@0 { #address-cells = <1>; #size-cells = <0>; + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + wakeup-source; + }; + pm8450a_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>;