From patchwork Thu Dec 15 15:10:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 634256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 237EFC4167B for ; Thu, 15 Dec 2022 15:12:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229624AbiLOPME (ORCPT ); Thu, 15 Dec 2022 10:12:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230080AbiLOPLv (ORCPT ); Thu, 15 Dec 2022 10:11:51 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6955A3055D; Thu, 15 Dec 2022 07:11:45 -0800 (PST) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BFE6fwu017300; Thu, 15 Dec 2022 15:11:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=8O+QTXU6K0VLHiPY0M+KwUb71ZkMEdSLJ8ngjTRFyuo=; b=I5yY8PHDhp6PlVPwEEWoyvQl7hS1jG+txYlyq4LuTf2ijPA9/gif5a2qjiJGX6ljGt7Q JlFLXQ7lIAUFV0vD+QUFtwiksvWdCEej5Dh6QsczTsjUhtbxaSMdWWxuw+787XVtEgxo Ggft1LJ6cVcQ+BbPsOfdOXoIztP0bH763CTBQtIBi/TMp4j2tbkFPh/j7gXcttZyPO7x O2qzw2c7hf459rr0kC0O7VosEkJrCW3kwUNIqHu11hyVdyoNLo9uJZiVR1ByIHLBSpEw zQWH20FGnUFV4EwGuloRViAabjkuKiZ2yQMPiLifznDuWwKDPmIS/XXgcdfz1Xm2xN71 Xw== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mfxse9dp7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Dec 2022 15:11:34 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BFFBX3l024897 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Dec 2022 15:11:33 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 15 Dec 2022 07:11:29 -0800 From: Akhil P Oommen To: freedreno , , , Rob Clark , Ulf Hansson , Bjorn Andersson CC: Akhil P Oommen , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , , Subject: [PATCH 2/5] clk: qcom: gdsc: Support 'synced_poweroff' genpd flag Date: Thu, 15 Dec 2022 20:40:58 +0530 Message-ID: <20221215203751.2.Ic128c1df50b7fc9a6b919932a3b41a799b5ed5e8@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1671117062-26276-1-git-send-email-quic_akhilpo@quicinc.com> References: <1671117062-26276-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: vs2Lql3VQhP6jb_phHc5QEzo2fnlkxVT X-Proofpoint-GUID: vs2Lql3VQhP6jb_phHc5QEzo2fnlkxVT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-15_08,2022-12-15_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 clxscore=1015 spamscore=0 phishscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212150123 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for the newly added 'synced_poweroff' genpd flag. This allows some clients (like adreno gpu driver) to request gdsc driver to ensure a votable gdsc (like gpucc cx gdsc) has collapsed at hardware. Signed-off-by: Akhil P Oommen --- drivers/clk/qcom/gdsc.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 9e4d6ce891aa..575019ba4768 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -136,7 +136,8 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool val) return 0; } -static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) +static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status, + bool force_sync) { int ret; @@ -149,7 +150,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF); /* If disabling votable gdscs, don't poll on status */ - if ((sc->flags & VOTABLE) && status == GDSC_OFF) { + if ((sc->flags & VOTABLE) && status == GDSC_OFF && !force_sync) { /* * Add a short delay here to ensure that an enable * right after it was disabled does not put it in an @@ -275,7 +276,7 @@ static int gdsc_enable(struct generic_pm_domain *domain) gdsc_deassert_clamp_io(sc); } - ret = gdsc_toggle_logic(sc, GDSC_ON); + ret = gdsc_toggle_logic(sc, GDSC_ON, false); if (ret) return ret; @@ -352,7 +353,7 @@ static int gdsc_disable(struct generic_pm_domain *domain) if (sc->pwrsts == PWRSTS_RET_ON) return 0; - ret = gdsc_toggle_logic(sc, GDSC_OFF); + ret = gdsc_toggle_logic(sc, GDSC_OFF, domain->synced_poweroff); if (ret) return ret; @@ -392,7 +393,7 @@ static int gdsc_init(struct gdsc *sc) /* Force gdsc ON if only ON state is supported */ if (sc->pwrsts == PWRSTS_ON) { - ret = gdsc_toggle_logic(sc, GDSC_ON); + ret = gdsc_toggle_logic(sc, GDSC_ON, false); if (ret) return ret; }