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[83.9.1.44]) by smtp.gmail.com with ESMTPSA id u14-20020a2e91ce000000b00279a7266874sm213830ljg.98.2022.12.13.02.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 02:43:36 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: qcom: dispcc-sm6115: Shrink single-parent definitions Date: Tue, 13 Dec 2022 11:43:33 +0100 Message-Id: <20221213104333.27548-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There's no need to provide both a parent map and a parent data struct when there's precisely a single parent. Collapse this to save a few bytes. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sm6115.c | 30 ++++++++---------------------- 1 file changed, 8 insertions(+), 22 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c index 818bb8f4637c..a6105033ff7e 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -103,14 +103,6 @@ static const struct clk_parent_data disp_cc_parent_data_0[] = { { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, }; -static const struct parent_map disp_cc_parent_map_1[] = { - { P_BI_TCXO, 0 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_1[] = { - { .index = DT_BI_TCXO }, -}; - static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 4 }, @@ -141,14 +133,6 @@ static const struct clk_parent_data disp_cc_parent_data_4[] = { { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, }; -static const struct parent_map disp_cc_parent_map_5[] = { - { P_SLEEP_CLK, 0 }, -}; - -static const struct clk_parent_data disp_cc_parent_data_5[] = { - { .index = DT_SLEEP_CLK, }, -}; - static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .cmd_rcgr = 0x20bc, .mnd_width = 0, @@ -284,12 +268,13 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .cmd_rcgr = 0x20a4, .mnd_width = 0, .hid_width = 5, - .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", - .parent_data = disp_cc_parent_data_1, - .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -304,12 +289,13 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = { .cmd_rcgr = 0x6050, .mnd_width = 0, .hid_width = 5, - .parent_map = disp_cc_parent_map_5, .freq_tbl = ftbl_disp_cc_sleep_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_sleep_clk_src", - .parent_data = disp_cc_parent_data_5, - .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), + .parent_data = &(const struct clk_parent_data){ + .index = DT_SLEEP_CLK, + }, + .num_parents = 1, .ops = &clk_rcg2_ops, }, };