| Message ID | 20221212133303.39610-4-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/4] arm64: dts: qcom: sc7180: correct SPMI bus address cells | expand |
Quoting Krzysztof Kozlowski (2022-12-12 05:33:02) > The Always On Subsystem (AOSS) QMP is not a power domain controller > since commit 135780456218 ("arm64: dts: qcom: sc7180: Use QMP property > to control load state") and few others. In fact, it was never a power > domain controller but rather control of power state of remote > processors. This power state control is know handled differently, thus > the AOSS QMP nodes do not have power-domain-cells: > > sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property > From schema: Documentation/devicetree/bindings/power/power-domain.yaml > > AOSS QMP is an interface to the actuall AOSS subsystem responsible for > some of power management functions, thus let's call the nodes as "pmu" - > Power Management Unit. Isn't 'pmu' a performance monitoring unit?
On 12/12/2022 20:08, Stephen Boyd wrote: > Quoting Krzysztof Kozlowski (2022-12-12 05:33:02) >> The Always On Subsystem (AOSS) QMP is not a power domain controller >> since commit 135780456218 ("arm64: dts: qcom: sc7180: Use QMP property >> to control load state") and few others. In fact, it was never a power >> domain controller but rather control of power state of remote >> processors. This power state control is know handled differently, thus >> the AOSS QMP nodes do not have power-domain-cells: >> >> sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property >> From schema: Documentation/devicetree/bindings/power/power-domain.yaml >> >> AOSS QMP is an interface to the actuall AOSS subsystem responsible for >> some of power management functions, thus let's call the nodes as "pmu" - >> Power Management Unit. > > Isn't 'pmu' a performance monitoring unit? No. PMU is whatever you call it... ARM calls it Performance Monitoring Unit, Samsung and Rockchip (and maybe others) call it Power Management Unit. It's just an acronym. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 906fb9343bcc..7e781570b2c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3248,7 +3248,7 @@ aoss_reset: reset-controller@c2a0000 { #reset-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: pmu@c300000 { compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7c24c2129800..b08ddeb7bcec 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4257,7 +4257,7 @@ aoss_reset: reset-controller@c2a0000 { #reset-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: pmu@c300000 { compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 3cb4ca6c53eb..e04f1f751881 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1921,7 +1921,7 @@ tsens1: thermal-sensor@c265000 { #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: pmu@c300000 { compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5f1f7cb52c90..2e15a003825e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4965,7 +4965,7 @@ aoss_reset: reset-controller@c2a0000 { #reset-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: pmu@c300000 { compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 0f01ff4feb55..bb20fed0f4f0 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1273,7 +1273,7 @@ tsens1: thermal-sensor@c265000 { #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: pmu@c300000 { compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x1000>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index d1b64280ab0b..ad6902b13a71 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3589,7 +3589,7 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: pmu@c300000 { compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index fbbbae29e0c2..6faf13ed90c1 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3741,7 +3741,7 @@ tsens1: thermal-sensor@c265000 { #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: pmu@c300000 { compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 49db223a0777..519e436aeab9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1717,7 +1717,7 @@ tsens1: thermal-sensor@c265000 { #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: pmu@c300000 { compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index e0d30dadbf8b..234fe6549fe0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2453,7 +2453,7 @@ tsens1: thermal-sensor@c265000 { #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: pmu@c300000 { compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
The Always On Subsystem (AOSS) QMP is not a power domain controller since commit 135780456218 ("arm64: dts: qcom: sc7180: Use QMP property to control load state") and few others. In fact, it was never a power domain controller but rather control of power state of remote processors. This power state control is know handled differently, thus the AOSS QMP nodes do not have power-domain-cells: sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property From schema: Documentation/devicetree/bindings/power/power-domain.yaml AOSS QMP is an interface to the actuall AOSS subsystem responsible for some of power management functions, thus let's call the nodes as "pmu" - Power Management Unit. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-)