| Message ID | 20221202155738.383301-3-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v3,1/3] arm64: dts: qcom: sdm845-db845c: fix audio codec interrupt pin name | expand |
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e6019009533e..1a7999843dd6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2785,8 +2785,6 @@ qup_i2c15_default: qup-i2c15-default-state { qup_spi0_default: qup-spi0-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup0"; - drive-strength = <6>; - bias-disable; }; qup_spi1_default: qup-spi1-default-state {
Each board should define pin drive/bias for used busses. All boards using SPI0 (db845c and cheza) already do it, so drop the bias/drive strength from SoC DTSI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Cc: Doug Anderson <dianders@chromium.org> Changes since v2: 1. New patch. --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 -- 1 file changed, 2 deletions(-)