From patchwork Tue Nov 29 20:46:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 629186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDC1CC4167B for ; Tue, 29 Nov 2022 20:47:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236699AbiK2UrY (ORCPT ); Tue, 29 Nov 2022 15:47:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236609AbiK2UrS (ORCPT ); Tue, 29 Nov 2022 15:47:18 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48A92264AE; Tue, 29 Nov 2022 12:47:16 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id b3so23907052lfv.2; Tue, 29 Nov 2022 12:47:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Ma9RUQu1JjVVoYty/WmEXDnYuOfQCd9ANuJ3pmUfPM=; b=T/qBBnIruUH/GUG83CcB0NngH2JXSmSIG9cGLShPtFZWw6A4daVJUvP6xwkdgAaFQW MGvObW7ShX2GrYtOjmizAfsy0e0PCGnYrb2D9M3OZ3dGGNnCM4wSQi3G1Adhteesiyvt BWfmhrLjUDB+LLFiRrgcXMksdn2nrX6rwVhuaYUWRubAHBu0FAhONOelr2nAsxzEzVVE xuFF7N/TdqngKU7p5vmUhzd7CEVprhegjCVeT16r9T1HabdsApxZicqPvon1Jxtam2pq PBJkp6LHq5tIzkAdJkq4zq/+nWn4icmNYzOVmrP1F82YW6mYhj8QVYVHRVbgQCdXneLL Wscg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Ma9RUQu1JjVVoYty/WmEXDnYuOfQCd9ANuJ3pmUfPM=; b=cbHW9YUP9cie7prKr660KopB/qavM2rDobjhB1CQB3VZ7FNO1jpf67XUpyGgElH1Kf 6fsb6zTTLqp+hHfY0Qsdv9f6PI1xC9G9XE2DbOOWZS52VpDYBWB2gdsfOo+ROhrOk56X ak3DEHimwUqA2dJNiSDSaBBOD56/H7xI000eoyC8XRoDcMrovUs6Dom3nnxp/DFgNq/6 IwRq9Tnm5k/1acC1My0rMEuLh18Pu6oO6Z99bp5sbaogPE9gvX0p4zDnP4TibRZksSLh a6kXJGzPIDSBt3sn+sXi/82HjCFHRB52c1fmbaLqiRFBowvOq8pypVvciAGye5JVh0dI cqKA== X-Gm-Message-State: ANoB5plek2aCVgR+f+r5frcK2GcxrhpIXeLeGBF3U5CzLzpDd4ACUzp9 KWuaJWF5Oo2GPCNHmIHSVGcdIQhwos0= X-Google-Smtp-Source: AA0mqf4vieHe53nkDLyouG86tJoxjWakBPNUKhkxYRv0lFIj9pr6eplRQSRLVtOwCbUFwy+SymcKLA== X-Received: by 2002:a19:5211:0:b0:4b5:1e6f:c9d3 with SMTP id m17-20020a195211000000b004b51e6fc9d3mr2074160lfb.659.1669754834500; Tue, 29 Nov 2022 12:47:14 -0800 (PST) Received: from localhost.localdomain (ccy110.neoplus.adsl.tpnet.pl. [83.30.148.110]) by smtp.gmail.com with ESMTPSA id o11-20020ac24e8b000000b004ae24368195sm2325620lfr.233.2022.11.29.12.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:47:14 -0800 (PST) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Loic Poulain , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 10/12] arm64: dts: qcom: sm6115: Add i2c/spi nodes Date: Tue, 29 Nov 2022 21:46:14 +0100 Message-Id: <20221129204616.47006-11-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221129204616.47006-1-a39.skl@gmail.com> References: <20221129204616.47006-1-a39.skl@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add I2C/SPI nodes for SM6115. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 287 +++++++++++++++++++++++++++ 1 file changed, 287 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index e9de7aa1efdd..d14a4595be8a 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -357,6 +358,90 @@ tlmm: pinctrl@500000 { interrupt-controller; #interrupt-cells = <2>; + qup_i2c0_default: qup-i2c0-default { + pins = "gpio0", "gpio1"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default { + pins = "gpio4", "gpio5"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default { + pins = "gpio6", "gpio7"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default { + pins = "gpio8", "gpio9"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default { + pins = "gpio14", "gpio15"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default { + pins = "gpio0", "gpio1","gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_default: qup-spi1-default { + pins = "gpio4", "gpio5", "gpio69", "gpio70"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_default: qup-spi2-default { + pins = "gpio6", "gpio7", "gpio71", "gpio80"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_default: qup-spi3-default { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_default: qup-spi4-default { + pins = "gpio12", "gpio13", "gpio96", "gpio97"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi5_default: qup-spi5-default { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -693,6 +778,208 @@ gpi_dma0: dma-controller@4a00000 { status = "disabled"; }; + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x04ac0000 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <1>; + #size-cells = <1>; + iommus = <&apps_smmu 0xe3 0x0>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x04a80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = ; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x04a84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = ; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x04a88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_default>; + interrupts = ; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_default>; + interrupts = ; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@4a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x04a8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_default>; + interrupts = ; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = ; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@4a90000 { + compatible = "qcom,geni-spi"; + reg = <0x04a90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + interrupts = ; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = ; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x04a94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_default>; + interrupts = ; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; reg = <0x04ef8800 0x400>;