From patchwork Mon Nov 28 12:28:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 629614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A835FC433FE for ; Mon, 28 Nov 2022 12:28:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230280AbiK1M2n (ORCPT ); Mon, 28 Nov 2022 07:28:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230321AbiK1M2l (ORCPT ); Mon, 28 Nov 2022 07:28:41 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1221BDFE8 for ; Mon, 28 Nov 2022 04:28:40 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id v1so16504284wrt.11 for ; Mon, 28 Nov 2022 04:28:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hehlayLfD+VpoMaqp50JltEW9ZOkwoZi8i1XpqkJ+jY=; b=BzPhIqc/BTGGhpONND2yBKDMSfQluG1Xwx+iM/D1FrsrEbITOBKG6SEmO4ICwQRqUD D8aNBxfggp19UmXMeigTfLEvVgEMkfJvTditF1F4IPAZVZ0dQF/RbHomju8o6JiQdwt8 ZKUj22KfMaipFplfD929PnusCr2PkRT9VcVkEOpy2aOUfvD4b+czBPWdkbUnMZ83ms/T uBrRfHj4XPQ2ceF7Nk1jSqg272a3pUq9IA1jr8MMkRqepYTpwfTCMYi5WK2DpDfMRr2a SnUH4ZUq0EkhhtzCmvHNEJq0+aciMfNS4ISbUCI4GAp68qahC03XkkH0+mwk/mfgC8zY LxqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hehlayLfD+VpoMaqp50JltEW9ZOkwoZi8i1XpqkJ+jY=; b=cdhYq7bctmVAjaSURVjn6BjcUCsw3+ETYW9VJSdKPqGcRihvs26YLGWCj1D4ptNYwt Yl0L9UakMj2nan/yhTAbz8aMXr+7Guda4YnMI07BlE2QHn8xlTzdo2CRK7Q2ic5htJdY TQRLLI3TR5Ddw6d5kTvraAzlRZM6Myf5wM8hFY6yLvhlFYU2gkTa20BRnWS2AlF1Xamy nYUxgbe1zcKqWI1fLaIHuzQoeOGhNlQ+g34q4I4ebeO/JBjFszS6g04zaop6VaPASwLk LGdHyRB5sc4p+E6DHtlBWnFeXTB/GFyk9z3aVVszlzvv4JnSf9fKgbDMxPN7ITZ1uMaC 4neQ== X-Gm-Message-State: ANoB5pmMqIHVhYG9tMx6ZCh037ZmaEpJhqY14c9GMJf/4ZEVbdgEklxf PInxwrzDCCodUxFSolAqfcUtKA== X-Google-Smtp-Source: AA0mqf6sMW1+jLzEM3Ft32N1rW0Q0NaUv7OJWoa14USXbzg+1voWzb1fg8lBNgB67iVc8nzw+3txjg== X-Received: by 2002:a5d:4281:0:b0:22e:3c69:f587 with SMTP id k1-20020a5d4281000000b0022e3c69f587mr24480414wrq.670.1669638518547; Mon, 28 Nov 2022 04:28:38 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id u18-20020adfdd52000000b002421db5f279sm598405wrm.78.2022.11.28.04.28.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 04:28:38 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mike Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 4/9] clk: qcom: Add LUCID_OLE PLL type for SM8550 Date: Mon, 28 Nov 2022 14:28:15 +0200 Message-Id: <20221128122820.798610-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128122820.798610-1-abel.vesa@linaro.org> References: <20221128122820.798610-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a LUCID_OLE PLL type for SM8550 SoC from Qualcomm. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 5 +++++ 2 files changed, 21 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 1973d79c9465..f9e4cfd7261c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -155,6 +155,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { + [PLL_OFF_OPMODE] = 0x04, + [PLL_OFF_STATE] = 0x08, + [PLL_OFF_STATUS] = 0x0c, + [PLL_OFF_L_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL] = 0x14, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0x1c, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_CONFIG_CTL_U1] = 0x28, + [PLL_OFF_TEST_CTL] = 0x2c, + [PLL_OFF_TEST_CTL_U] = 0x30, + [PLL_OFF_TEST_CTL_U1] = 0x34, + [PLL_OFF_TEST_CTL_U2] = 0x38, + }, [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { [PLL_OFF_OPMODE] = 0x04, [PLL_OFF_STATUS] = 0x0c, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index f9524b3fce6b..2bdae362c827 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -18,6 +18,7 @@ enum { CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_LUCID_EVO, + CLK_ALPHA_PLL_TYPE_LUCID_OLE, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, @@ -38,6 +39,8 @@ enum { PLL_OFF_TEST_CTL, PLL_OFF_TEST_CTL_U, PLL_OFF_TEST_CTL_U1, + PLL_OFF_TEST_CTL_U2, + PLL_OFF_STATE, PLL_OFF_STATUS, PLL_OFF_OPMODE, PLL_OFF_FRAC, @@ -160,7 +163,9 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops; extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; +#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; +#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops