From patchwork Tue Nov 22 10:21:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 628026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B04B6C43219 for ; Tue, 22 Nov 2022 10:22:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233472AbiKVKW1 (ORCPT ); Tue, 22 Nov 2022 05:22:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232819AbiKVKVy (ORCPT ); Tue, 22 Nov 2022 05:21:54 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C304205C2 for ; Tue, 22 Nov 2022 02:21:45 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id b12so10176444wrn.2 for ; Tue, 22 Nov 2022 02:21:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7EJrTQIS5zIHcJVe/CbMMVgFbpImlTtQ6/Fo8uf0cQs=; b=FYfzwS4CBrRcXV5ZFnLGwjwIz55YZzRUisru4kJviiTfhx0Xb7YABMkuRTXPsZQtuZ Tgl+WByJ+uyYYK4OhOAotaGNnq5eawB9MQ7SzTc2PqanALdWpXM5uvw+U++3rjvruaVc UnlpPICZ2pLTyb/GWYXsKowF2O7698PNkDgCMiX0yrA3+NmSajm7YgRohZgmIcbm4t7p RjFFyr5yBvekdoQgybn0OQzdPNlp+ilYm2ahefYR5hDjRqQZxrk4O2hwQpWv1ka+jbAA leihr0Z3RpKbmLuhIaXy3omF+C1kWJ0KQoyFpTNy+508uT0DJKmuxpUKQfFjHwmJW/x/ eGXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7EJrTQIS5zIHcJVe/CbMMVgFbpImlTtQ6/Fo8uf0cQs=; b=0T9c7H9cMxy+I3UIhbEx1okOmb3y4CYxZEcm11Y4XMVEMsou5u3Gi5MYtBc4IkI1Qp XFekOLJlfQZJGg93qaPeUE1D0kWTr5QPVtAUpE/tPx+kr62XymMlGieTW+BXgIVeblkf jPHcIrVHra9+WJIQRKyuFqBBFQgLDDfh3f1JDmPpmVgd88lYEFmoSkI2ohg0LtvhGbff UDo7gw1TKtUNwo3m4v1Fn9zcNbaeRbdv+bY3sN2KhexzpAggrXRtjZLmU81QNzTc/X76 lCIPeXtMNlOXhiJF5S/bEvft/MQq1dkjO7G6eJwb72ISlvglMXG+AqmX1UtnrU9K5x5P 71CA== X-Gm-Message-State: ANoB5pkVkZh1xudrzbchzyNDcELyE7JEEJMO239yXw8DSQ1VRx58vByG rGMN12nZuZfJClN+5Uzv7by0jw== X-Google-Smtp-Source: AA0mqf67QEyEJPYa/qS7uOsPGrGtvHyweo/xX/z+5S9QkzWHxxr4eJ+2ayueoMezsRbkHG6APMIBUQ== X-Received: by 2002:adf:e190:0:b0:241:d451:7fc9 with SMTP id az16-20020adfe190000000b00241d4517fc9mr3861780wrb.223.1669112503975; Tue, 22 Nov 2022 02:21:43 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:e011:9e81:66f1:3415]) by smtp.gmail.com with ESMTPSA id o3-20020a5d4083000000b002366e8eee11sm13432873wrp.101.2022.11.22.02.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 02:21:43 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Srinivas Kandagatla , Vinod Koul , Alex Elder , =?utf-8?q?Ilp?= =?utf-8?q?o_J=C3=A4rvinen?= Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, Bartosz Golaszewski , Konrad Dybcio Subject: [PATCH v2 03/15] tty: serial: qcom-geni-serial: align #define values Date: Tue, 22 Nov 2022 11:21:13 +0100 Message-Id: <20221122102125.142075-4-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221122102125.142075-1-brgl@bgdev.pl> References: <20221122102125.142075-1-brgl@bgdev.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bartosz Golaszewski Keep the #define symbols aligned for better readability. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- drivers/tty/serial/qcom_geni_serial.c | 62 +++++++++++++-------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 7af5df6833c7..97ee7c074b79 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -39,57 +39,57 @@ #define SE_UART_MANUAL_RFR 0x2ac /* SE_UART_TRANS_CFG */ -#define UART_TX_PAR_EN BIT(0) -#define UART_CTS_MASK BIT(1) +#define UART_TX_PAR_EN BIT(0) +#define UART_CTS_MASK BIT(1) /* SE_UART_TX_STOP_BIT_LEN */ -#define TX_STOP_BIT_LEN_1 0 -#define TX_STOP_BIT_LEN_2 2 +#define TX_STOP_BIT_LEN_1 0 +#define TX_STOP_BIT_LEN_2 2 /* SE_UART_RX_TRANS_CFG */ -#define UART_RX_PAR_EN BIT(3) +#define UART_RX_PAR_EN BIT(3) /* SE_UART_RX_WORD_LEN */ -#define RX_WORD_LEN_MASK GENMASK(9, 0) +#define RX_WORD_LEN_MASK GENMASK(9, 0) /* SE_UART_RX_STALE_CNT */ -#define RX_STALE_CNT GENMASK(23, 0) +#define RX_STALE_CNT GENMASK(23, 0) /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ -#define PAR_CALC_EN BIT(0) -#define PAR_EVEN 0x00 -#define PAR_ODD 0x01 -#define PAR_SPACE 0x10 +#define PAR_CALC_EN BIT(0) +#define PAR_EVEN 0x00 +#define PAR_ODD 0x01 +#define PAR_SPACE 0x10 /* SE_UART_MANUAL_RFR register fields */ -#define UART_MANUAL_RFR_EN BIT(31) -#define UART_RFR_NOT_READY BIT(1) -#define UART_RFR_READY BIT(0) +#define UART_MANUAL_RFR_EN BIT(31) +#define UART_RFR_NOT_READY BIT(1) +#define UART_RFR_READY BIT(0) /* UART M_CMD OP codes */ -#define UART_START_TX 0x1 +#define UART_START_TX 0x1 /* UART S_CMD OP codes */ -#define UART_START_READ 0x1 - -#define UART_OVERSAMPLING 32 -#define STALE_TIMEOUT 16 -#define DEFAULT_BITS_PER_CHAR 10 -#define GENI_UART_CONS_PORTS 1 -#define GENI_UART_PORTS 3 -#define DEF_FIFO_DEPTH_WORDS 16 -#define DEF_TX_WM 2 -#define DEF_FIFO_WIDTH_BITS 32 -#define UART_RX_WM 2 +#define UART_START_READ 0x1 + +#define UART_OVERSAMPLING 32 +#define STALE_TIMEOUT 16 +#define DEFAULT_BITS_PER_CHAR 10 +#define GENI_UART_CONS_PORTS 1 +#define GENI_UART_PORTS 3 +#define DEF_FIFO_DEPTH_WORDS 16 +#define DEF_TX_WM 2 +#define DEF_FIFO_WIDTH_BITS 32 +#define UART_RX_WM 2 /* SE_UART_LOOPBACK_CFG */ -#define RX_TX_SORTED BIT(0) -#define CTS_RTS_SORTED BIT(1) -#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) +#define RX_TX_SORTED BIT(0) +#define CTS_RTS_SORTED BIT(1) +#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) /* UART pin swap value */ -#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) +#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) #define IO_MACRO_IO0_SEL 0x3 -#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) +#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) #define IO_MACRO_IO2_IO3_SWAP 0x4640 /* We always configure 4 bytes per FIFO word */