From patchwork Fri Nov 18 23:32:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 626899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55A19C4321E for ; Sat, 19 Nov 2022 00:10:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237583AbiKSAKG (ORCPT ); Fri, 18 Nov 2022 19:10:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237167AbiKSAJj (ORCPT ); Fri, 18 Nov 2022 19:09:39 -0500 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC306A13C9 for ; Fri, 18 Nov 2022 15:32:57 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id g12so10649790lfh.3 for ; Fri, 18 Nov 2022 15:32:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1xDiE8Bwh4Ikzuy5U7/SCqTlGH/WFHTyDSOulj4Kkk0=; b=JJ6v0JJYYWa8jgUBtPN9xCyQne9val3S1YfDZFMue7laW/7FIVlJV6474jkssWN+ZR nx8RCCT7LEG3R3cmEPrevcC/tdsrynQPLaip+Yt0Ajkp7JokPHbfxtprERYyDbgQapW2 2j6318UQNiwIwJFQBXurAdNyuR5GX8r3lklPkl8nDlfj49f6u2geW9kyOsnUk+GIW5Zq ytLi75CuSKcnIj/pYh1XqWLd9YlTIz1IDcm7IConLOak5Z0HBadL41Nlex4HemMsOEEJ 9DDMM3FueHhAkT0q1WKmuN0sv6QFJQXjJQjdqXGpNtU8LH6IEHVctSL+eRQFfsNJpchP oBLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1xDiE8Bwh4Ikzuy5U7/SCqTlGH/WFHTyDSOulj4Kkk0=; b=wPwcBccgyxJCTzb5BiC3DFba5e/rLsqycJWm0khQAbAS+YKVw2eVaFMEQjXyc3ZypM /RL0n9K0P69Xu+3v6D15lo0lBCAjLm/9hGc3dYhcA7/YKksXrDwaYdMLQfMy4oYYVH9P 1d8htRMC1cWT5/jaQaJ7AS0KsJu2FvQFeW+fyuWO11k6F6X5bimkdSXEdUP98oB2JD4B XRa/8kIekcDwSRJAAOWVCPR6z8OpOxjvMvws6RGh9LDkJKUNezrgg6/zw3sZcUh7WcE3 w3ToQpkXtECNCeP/FUldTy605XyRbQzsTAz9mQfzIp3Y9lUIwXBZPoron7rAyPNUJmtt Makw== X-Gm-Message-State: ANoB5pkj+fMp+2VQLzB5mpvHoAOQECrDxmDS45whgeW8TFt0cEcjb2Rb MCNi7giuismEasvFIHwDvTYD5Q== X-Google-Smtp-Source: AA0mqf5YxhcVuevI0EQUNPCzj+Zpxr7hOfRkWCHRK+XogwQMTUTpF8SHlglkdVLQfR/srYQmyXkAKA== X-Received: by 2002:ac2:5455:0:b0:4a2:2d58:1a12 with SMTP id d21-20020ac25455000000b004a22d581a12mr3005429lfn.94.1668814375960; Fri, 18 Nov 2022 15:32:55 -0800 (PST) Received: from eriador.lumag.spb.ru ([194.204.33.9]) by smtp.gmail.com with ESMTPSA id k13-20020ac257cd000000b004947f8b6266sm843900lfo.203.2022.11.18.15.32.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 15:32:55 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v4 5/8] phy: qcom-qmp-pcie: rename the sm8450 gen3 PHY config tables Date: Sat, 19 Nov 2022 01:32:39 +0200 Message-Id: <20221118233242.2904088-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> References: <20221118233242.2904088-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SM8350 PHY config tables are mostly the same as SM8450 gen3 PHY config tables. Rename generic tables to remove x1 suffix. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index d9f8dffbe1da..4a55b2439952 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1218,7 +1218,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), }; -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { +static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), @@ -1274,7 +1274,7 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), }; -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { +static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), @@ -1302,7 +1302,7 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), }; -static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { +static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), @@ -2025,14 +2025,14 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { .lanes = 1, .tbls = { - .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, - .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), + .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), - .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, - .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), - .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, - .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), + .rx = sm8450_qmp_gen3_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), + .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), },