From patchwork Fri Nov 18 12:25:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 626192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02CBEC4332F for ; Fri, 18 Nov 2022 12:26:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241571AbiKRM0I (ORCPT ); Fri, 18 Nov 2022 07:26:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241437AbiKRM0H (ORCPT ); Fri, 18 Nov 2022 07:26:07 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5D0F9737D for ; Fri, 18 Nov 2022 04:26:06 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id y16so8983014wrt.12 for ; Fri, 18 Nov 2022 04:26:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ix98Buqrm8hc4zZgibw2ROra30KJmpCLaRPoOVSax6U=; b=fr2y+fgpu7yMtDfL/F6WHS15il9rZPexAjvuSgluGk58Q50xnOVM6u6jOY/KO/1xsY z0h4BK4SSg7EJEYSkG0kxrjxd1rgA+X6ACOkAllPjRlzpLsrQq0hvwHKvHKHJuOR5xU2 cZzLi6EJWcv5J0IkgWUjzxMJMKjT9OYRPIs5OE0izDQEyfjW1RzYl6QriSImMbbaYz+a 5+TVTTdxVl8vu0gTd84Is720pu7ojdK4DjYoPZxYWz3YB9KwsD0iT8Jt7cPDjEnwXfE1 /8UwXwEItbZYJxEGYmqU+eTGqdPED/DcOQ5nZ/yf6Zi90pQJuD7R8aumxus6kn1JyLm4 MnKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ix98Buqrm8hc4zZgibw2ROra30KJmpCLaRPoOVSax6U=; b=RIk/fpZDxWDsDzFCcrZEeOP7LSw9hlaunhRamQxoS+L1UqwirsTqkZkuJ7B5e0X4DI r4h6RPfFUNIlssbuXuHh1bvKoO5XA70o9PxucGspHXHjJ7BiD93puFjgMLn2WlXi6+Um bVH6l3JI73gprBrEFUIzQfaK4gL+nl1bQE7bxtKUgn/fDpkJGys7Nv/vW7n4JGUANYL5 xETEG4FUZV7wTc5td/i+ZmHqztf2t0AQSpyMGH2cfcElrxP1Thkf+d/18r/icUgUjx/D wSo1LAIlKgn7gPvaBRn+fFMLieAN8PwgZODgejPpyGf6F8bkPdmxjuF3Wk6QJvxYthAn r9gg== X-Gm-Message-State: ANoB5plBt29694OtclnnxfNR7Tl0eaKWx5ZG1PYoiqUyuXi+74tP+YWf ZMDsYDXVDi+fsuTLmJWccISjBg== X-Google-Smtp-Source: AA0mqf4w0Sogr6egE1uHzDv9Nl0SENIbQJhiBOjTBFjUjGbvkSUShCyBnX0yw4Jf9SDeOD3OxkfGuw== X-Received: by 2002:a05:6000:1d94:b0:238:3d85:8e2c with SMTP id bk20-20020a0560001d9400b002383d858e2cmr4248475wrb.650.1668774365147; Fri, 18 Nov 2022 04:26:05 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:b10c:1279:a704:75d4]) by smtp.gmail.com with ESMTPSA id f19-20020a05600c155300b003c6f3e5ba42sm9873958wmg.46.2022.11.18.04.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 04:26:04 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Srinivas Kandagatla , Vinod Koul , Alex Elder Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH 03/15] tty: serial: qcom-geni-serial: align #define values Date: Fri, 18 Nov 2022 13:25:27 +0100 Message-Id: <20221118122539.384993-4-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221118122539.384993-1-brgl@bgdev.pl> References: <20221118122539.384993-1-brgl@bgdev.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bartosz Golaszewski Keep the #define symbols aligned for better readability. Signed-off-by: Bartosz Golaszewski --- drivers/tty/serial/qcom_geni_serial.c | 62 +++++++++++++-------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 7af5df6833c7..97ee7c074b79 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -39,57 +39,57 @@ #define SE_UART_MANUAL_RFR 0x2ac /* SE_UART_TRANS_CFG */ -#define UART_TX_PAR_EN BIT(0) -#define UART_CTS_MASK BIT(1) +#define UART_TX_PAR_EN BIT(0) +#define UART_CTS_MASK BIT(1) /* SE_UART_TX_STOP_BIT_LEN */ -#define TX_STOP_BIT_LEN_1 0 -#define TX_STOP_BIT_LEN_2 2 +#define TX_STOP_BIT_LEN_1 0 +#define TX_STOP_BIT_LEN_2 2 /* SE_UART_RX_TRANS_CFG */ -#define UART_RX_PAR_EN BIT(3) +#define UART_RX_PAR_EN BIT(3) /* SE_UART_RX_WORD_LEN */ -#define RX_WORD_LEN_MASK GENMASK(9, 0) +#define RX_WORD_LEN_MASK GENMASK(9, 0) /* SE_UART_RX_STALE_CNT */ -#define RX_STALE_CNT GENMASK(23, 0) +#define RX_STALE_CNT GENMASK(23, 0) /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ -#define PAR_CALC_EN BIT(0) -#define PAR_EVEN 0x00 -#define PAR_ODD 0x01 -#define PAR_SPACE 0x10 +#define PAR_CALC_EN BIT(0) +#define PAR_EVEN 0x00 +#define PAR_ODD 0x01 +#define PAR_SPACE 0x10 /* SE_UART_MANUAL_RFR register fields */ -#define UART_MANUAL_RFR_EN BIT(31) -#define UART_RFR_NOT_READY BIT(1) -#define UART_RFR_READY BIT(0) +#define UART_MANUAL_RFR_EN BIT(31) +#define UART_RFR_NOT_READY BIT(1) +#define UART_RFR_READY BIT(0) /* UART M_CMD OP codes */ -#define UART_START_TX 0x1 +#define UART_START_TX 0x1 /* UART S_CMD OP codes */ -#define UART_START_READ 0x1 - -#define UART_OVERSAMPLING 32 -#define STALE_TIMEOUT 16 -#define DEFAULT_BITS_PER_CHAR 10 -#define GENI_UART_CONS_PORTS 1 -#define GENI_UART_PORTS 3 -#define DEF_FIFO_DEPTH_WORDS 16 -#define DEF_TX_WM 2 -#define DEF_FIFO_WIDTH_BITS 32 -#define UART_RX_WM 2 +#define UART_START_READ 0x1 + +#define UART_OVERSAMPLING 32 +#define STALE_TIMEOUT 16 +#define DEFAULT_BITS_PER_CHAR 10 +#define GENI_UART_CONS_PORTS 1 +#define GENI_UART_PORTS 3 +#define DEF_FIFO_DEPTH_WORDS 16 +#define DEF_TX_WM 2 +#define DEF_FIFO_WIDTH_BITS 32 +#define UART_RX_WM 2 /* SE_UART_LOOPBACK_CFG */ -#define RX_TX_SORTED BIT(0) -#define CTS_RTS_SORTED BIT(1) -#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) +#define RX_TX_SORTED BIT(0) +#define CTS_RTS_SORTED BIT(1) +#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) /* UART pin swap value */ -#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) +#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) #define IO_MACRO_IO0_SEL 0x3 -#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) +#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) #define IO_MACRO_IO2_IO3_SWAP 0x4640 /* We always configure 4 bytes per FIFO word */