From patchwork Tue Nov 15 15:58:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 478DFC43217 for ; Tue, 15 Nov 2022 15:58:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229791AbiKOP6h (ORCPT ); Tue, 15 Nov 2022 10:58:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238005AbiKOP62 (ORCPT ); Tue, 15 Nov 2022 10:58:28 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE8602E9EA for ; Tue, 15 Nov 2022 07:58:17 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id x102so7275115ede.0 for ; Tue, 15 Nov 2022 07:58:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=hGWW/MIEHrCQNewHhRIGxXTQAeOC4rpUnCL7BHFVFTI=; b=Lwa63gbzI5j9Db9s8Tqo3pXxDn8bTBGC+950ifG8Uz2bpbSF1oscH0frYnjYaR0ERK rDu3aYe+mm6brSi6rKtOcMBnJ9aG/H3G7JvqcGPn5GtdshRIgHy4g4hmF93ikZW4SVpA S69zH9z1s3Vfgxx16h6OQrZY0S7AR+Yso0IeaJmQNX5kFV8kpYNKE7Ru9QSKuorHdyes NwIhpnoBQbknI85fF5KIuFzVVcERf1c4v97jTRYlWJo4cyXXG+10oHZZCiVMEScM5el/ Gcl3jjD1tQCTTPVPgNU+lFj2mHwYv2xlruI3BlcfDHuMW5E1jPCPWAP1d+3absNiOqGs aVkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=hGWW/MIEHrCQNewHhRIGxXTQAeOC4rpUnCL7BHFVFTI=; b=Zf9NU0f1qHnXXASMa3gpBr7ZmpPhWCGweZcklMpBTfQpEn+TO0z0emUYY2hyZFOcVM MdtD4XUiCo/HtwoLm2DRDHmAEj5cKeMEzWIRmzZx/oTzIstWyItQIoaeh3/zlCOa762a dKqHKLrc3BJThztT21XVPWliHIv85x6Pb3plPzjeKtfdpUxGmR0qBmUAoyK38rdJI7mE 0EuMT8JlmqvE4AhLRdrBX67Yt32VNKYB/rDZ2CwQh5XlM5bTbromCNbAwdlMHK29CpU4 nIWhjllH3q2r/ZgUJ6OHPa/njQnpZbM3Vf5Du/Q3Sz7oBTqFrm/vtkyYYrGFedLMwjzQ T7Ig== X-Gm-Message-State: ANoB5pniBFXFFc+a4dB/uy3NdKDQnRW7WTLhBwq8vjdG+CwpDTDCMWiS QpPlqyohKB4GmnqK94EqfDxjPRNwA+WvcdfJ X-Google-Smtp-Source: AA0mqf7luJopzkTusEkfEOC8tAcynClaHNm8M2ztZoZ1CBg7umddLW94rNC65M0BYZxMvfKkgbqhTw== X-Received: by 2002:aa7:cd15:0:b0:458:5987:7203 with SMTP id b21-20020aa7cd15000000b0045859877203mr15005315edw.161.1668527896175; Tue, 15 Nov 2022 07:58:16 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id ky4-20020a170907778400b0077b523d309asm5648085ejc.185.2022.11.15.07.58.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Nov 2022 07:58:15 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: clock: add QCOM SM6375 display clock bindings Date: Tue, 15 Nov 2022 16:58:04 +0100 Message-Id: <20221115155808.10899-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6375 SoC. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio --- Changes in v2: - Switch to dual licensing in both files - Adjust the wording with the recent refactoring - use qcom,gcc.yaml for common properties .../bindings/clock/qcom,sm6375-dispcc.yaml | 54 +++++++++++++++++++ .../dt-bindings/clock/qcom,sm6375-dispcc.h | 42 +++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6375-dispcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml new file mode 100644 index 000000000000..183b1c75dbdf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM6375. + + See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,sm6375-dispcc + + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + + clock-controller@5f00000 { + compatible = "qcom,sm6375-dispcc"; + reg = <0x05f00000 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&dsi_phy 0>, + <&dsi_phy 1>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6375-dispcc.h b/include/dt-bindings/clock/qcom,sm6375-dispcc.h new file mode 100644 index 000000000000..1cb0bed004bd --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6375-dispcc.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6375_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6375_H + +/* Clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define DISP_CC_MDSS_ESC0_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK_SRC 8 +#define DISP_CC_MDSS_MDP_CLK 9 +#define DISP_CC_MDSS_MDP_CLK_SRC 10 +#define DISP_CC_MDSS_MDP_LUT_CLK 11 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12 +#define DISP_CC_MDSS_PCLK0_CLK 13 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 14 +#define DISP_CC_MDSS_ROT_CLK 15 +#define DISP_CC_MDSS_ROT_CLK_SRC 16 +#define DISP_CC_MDSS_RSCC_AHB_CLK 17 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 18 +#define DISP_CC_MDSS_VSYNC_CLK 19 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 20 +#define DISP_CC_SLEEP_CLK 21 +#define DISP_CC_XO_CLK 22 + +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +/* GDSCs */ +#define MDSS_GDSC 0 + +#endif