From patchwork Mon Nov 14 17:06:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 625705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E030C4321E for ; Mon, 14 Nov 2022 17:06:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238125AbiKNRGq (ORCPT ); Mon, 14 Nov 2022 12:06:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238017AbiKNRGp (ORCPT ); Mon, 14 Nov 2022 12:06:45 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB3082CE2F for ; Mon, 14 Nov 2022 09:06:43 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id be13so20341009lfb.4 for ; Mon, 14 Nov 2022 09:06:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BQ/MfRbWk57/TlYjqOkdCZzo+bH2efQi2zy0dipg9Lk=; b=Ybm3icAEX/zMCgQ96gcuMRHqFMY1zbO/o9KF4SClXRDcH1S2JPnFHAPvA/Z5CYln5B h6Nvc5dU4SLrW/s1zWPfliHpIifnJhRCmwpENHhMWSvBnZqXC91vIUl3CFloaFrQHVza LPZ8jR49+l5efLnmOVa5EuYGeBLKUCqjHrh9Kg4fV5d7xIx4vXfwgdjNLTqrhyRZrtLd gGS7JL3cqW3ZCEVcURJ0ocXbXTAVZ2YkiR0zCxSWi0f8ss0UrpwKoSXvBj8t1Vx7K70d 93m92seMkRhDoP19I/caurwPU/+GJ0VSasElNhl1RJRiCWrNEgIkVOBiR9TLZniTlh3N kYIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BQ/MfRbWk57/TlYjqOkdCZzo+bH2efQi2zy0dipg9Lk=; b=fwZxlyFdQETVbBaPjzlJPq0c3raDh74u84SbsbzQoUxWWjFrCoZGeqW0y6WWSsDio4 MlMECuf3R2iZd3EnmfPGso+3a16S8oWZnEz+L7Edx2HgqEEzCe0va/k7sz5Dk8BWaieM +4PAmOADB2LxFbla/4CQKoNVzPBHrMioMRBwYJfXJTJFEhHGXc1YeN3K9w9Ako41CXfx t6LQt9oJx795UYaxkQywvrhHMNSpgVQO7Bp7i2vHNSTmd/RiNTyNIrfttw2be9YNtct0 MDVypCPMnGnQDCYAXba9OmoJ/0301dtAZ6MWWjOTbei2iSSznhzyXGo3ceRb9GpD9gIP Cigw== X-Gm-Message-State: ANoB5pndBAcTUJbDK0dI/1hnmXAIigTAns3U/17KxHbQhVePlSVuVhRL j/2yBuZodXwp2X0knNhCK8pkVGEBzsp5pw== X-Google-Smtp-Source: AA0mqf4khZfwph7q3arr7F4lnxZ6eYoGK0PnPggZFqIpo12pvDxhIQKh5Umxfrue2P5ctwRC9Rp7/w== X-Received: by 2002:ac2:5f1a:0:b0:4b1:be16:4a4a with SMTP id 26-20020ac25f1a000000b004b1be164a4amr5035274lfq.0.1668445602169; Mon, 14 Nov 2022 09:06:42 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q7-20020a056512210700b004a2ae643b99sm1896344lfr.170.2022.11.14.09.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 09:06:41 -0800 (PST) From: Dmitry Baryshkov To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Clark Cc: Vinod Koul , Sai Prakash Ranjan , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [PATCH v1 07/10] iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500 Date: Mon, 14 Nov 2022 20:06:32 +0300 Message-Id: <20221114170635.1406534-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221114170635.1406534-1-dmitry.baryshkov@linaro.org> References: <20221114170635.1406534-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is only one platform, which needs special care in the reset function, the SDM845. Add special handler for sdm845 and drop the qcom_smmu500_reset() function. Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan Signed-off-by: Dmitry Baryshkov --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 37 +++++++++++++--------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index e61194127772..6dc7fa918799 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) { int ret; + arm_mmu500_reset(smmu); + /* * To address performance degradation in non-real time clients, * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, @@ -374,23 +376,20 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) return ret; } -static int qcom_smmu500_reset(struct arm_smmu_device *smmu) -{ - const struct device_node *np = smmu->dev->of_node; - - arm_mmu500_reset(smmu); - - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) - return qcom_sdm845_smmu500_reset(smmu); - - return 0; -} - static const struct arm_smmu_impl qcom_smmu_impl = { .init_context = qcom_smmu_init_context, .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, - .reset = qcom_smmu500_reset, + .reset = arm_mmu500_reset, + .write_s2cr = qcom_smmu_write_s2cr, + .tlb_sync = qcom_smmu_tlb_sync, +}; + +static const struct arm_smmu_impl sdm845_smmu_500_impl = { + .init_context = qcom_smmu_init_context, + .cfg_probe = qcom_smmu_cfg_probe, + .def_domain_type = qcom_smmu_def_domain_type, + .reset = qcom_sdm845_smmu500_reset, .write_s2cr = qcom_smmu_write_s2cr, .tlb_sync = qcom_smmu_tlb_sync, }; @@ -398,7 +397,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = { static const struct arm_smmu_impl qcom_adreno_smmu_impl = { .init_context = qcom_adreno_smmu_init_context, .def_domain_type = qcom_smmu_def_domain_type, - .reset = qcom_smmu500_reset, + .reset = arm_mmu500_reset, .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, .tlb_sync = qcom_smmu_tlb_sync, @@ -450,6 +449,14 @@ static const struct qcom_smmu_match_data qcom_smmu_data = { .adreno_impl = &qcom_adreno_smmu_impl, }; +static const struct qcom_smmu_match_data sdm845_smmu_500_data = { + .impl = &sdm845_smmu_500_impl, + /* + * No need for adreno impl here. On sdm845 the Adreno SMMU is handled + * by the separate sdm845-smmu-v2 device. + */ +}; + static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data }, { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data }, @@ -461,7 +468,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data }, { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data }, { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data }, - { .compatible = "qcom,sdm845-smmu-500", .data = &qcom_smmu_data }, + { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data }, { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_data }, { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data }, { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },