| Message ID | 20221109111236.46003-2-konrad.dybcio@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | SM6375/PDX225 GPI DMA, QUPs & PMIC peripherals | expand |
On 09/11/2022 12:12, Konrad Dybcio wrote: > Some SMMUs require that a vote is held on as much as 3 separate PDs > (hello Qualcomm). Allow it in bindings. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 9066e6df1ba1..1897d0d4d820 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -159,7 +159,7 @@ properties: > through the TCU's programming interface. > > power-domains: > - maxItems: 1 > + maxItems: 3 This is not correct - you now require 3 power domains everywhere. If you test the DTS you will notice it. You need min and max items, plus provably allOf:if:then restricting it per some variants (if it makes sense... depends which SMMUs need it). Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 9066e6df1ba1..1897d0d4d820 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -159,7 +159,7 @@ properties: through the TCU's programming interface. power-domains: - maxItems: 1 + maxItems: 3 nvidia,memory-controller: description: |
Some SMMUs require that a vote is held on as much as 3 separate PDs (hello Qualcomm). Allow it in bindings. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)