| Message ID | 20221027123432.1818530-2-robert.foss@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v1,1/5] clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350 | expand |
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 180ac2726f7e..a7606580cf22 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1137,7 +1137,7 @@ static struct gdsc mdss_gdsc = { .name = "mdss_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL, + .flags = HW_CTRL | RETAIN_FF_ENABLE, }; static struct clk_regmap *disp_cc_sm8250_clocks[] = {
All SoC supported by this driver supports the RETAIN_FF_ENABLE flag, so it should be enabled here. This feature enables registers to maintain their state after dis/re-enabling the GDSC. Signed-off-by: Robert Foss <robert.foss@linaro.org> --- drivers/clk/qcom/dispcc-sm8250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)