@@ -572,26 +572,6 @@ &spi10 {
&tlmm {
gpio-reserved-ranges = <28 4>;
- sdc2_default_state: sdc2-default-state {
- clk-pins {
- pins = "sdc2_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "sdc2_cmd";
- drive-strength = <16>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "sdc2_data";
- drive-strength = <16>;
- bias-pull-up;
- };
- };
-
ts_int_default: ts-int-default-state {
pins = "gpio23";
function = "gpio";
@@ -2515,6 +2515,26 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 211>;
wakeup-parent = <&pdc>;
+ sdc2_default_state: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
sdc2_sleep_state: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";
The SDHCI pin configuration/mux nodes are actually common to all upstreamed boards, so define them in SoC DTSI to reduce code duplication. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- In theory drive strength belongs to the board DTS, not SoC DTSI, but I am following the advice here: https://lore.kernel.org/lkml/CAD=FV=VUL4GmjaibAMhKNdpEso_Hg_R=XeMaqah1LSj_9-Ce4Q@mail.gmail.com/ --- .../qcom/sm8450-sony-xperia-nagara-pdx223.dts | 20 ------------------- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 +++++++++++++++++++ 2 files changed, 20 insertions(+), 20 deletions(-)