From patchwork Wed Oct 26 19:42:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 619621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B6B1C433FE for ; Wed, 26 Oct 2022 19:43:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233706AbiJZTnb (ORCPT ); Wed, 26 Oct 2022 15:43:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234629AbiJZTm4 (ORCPT ); Wed, 26 Oct 2022 15:42:56 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B343D106902 for ; Wed, 26 Oct 2022 12:42:37 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id d59-20020a17090a6f4100b00213202d77e1so3757288pjk.2 for ; Wed, 26 Oct 2022 12:42:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y45Z9F5+/R9uqywDzN7icoG5SzFxInaah2IApmdYfxw=; b=Iy9rHMtN9Rv2jganlhmWgo4QVH8Z7RUUGpg2ylFrGCK3WZN2XS7hhrGR9N3EkAipMB Iwx6g7aDxY2T1V1+Jm761uVArvrg2ri/fPYwbk0fiE4ko/o4cdje9BwYuxpIrfgvmK72 KB/rlobuS5mS4s+bNIjyb46By3UIsEOQ4qZwA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y45Z9F5+/R9uqywDzN7icoG5SzFxInaah2IApmdYfxw=; b=T0bHPB1VS/yhgRYbZK3xLv+qb1jKktzscuOOx2Xpcw6t3seOfQtVC1X9eTz5qM3vrL JKh516xM0yHlAUnyJihHfhIjIPfddZgB5xDdTo99fPBQHeanJ0f2Xxz8ZCfjkXA8KTh5 D8DkHRI1hub5GjvKX0aSQeGj6PA5B9aFgVK3WXZzq67hNZMxM+QQypFgV/jnEfsNFEcZ xUeYfLyAHNnYFpRDu6n0gD+yWiQ+pgcsaAklstWzkFwRjDO3ZCkZnB0ZGRIqSEALaiib Glq8mQQiIWh5ynFzgmcWizjTaZbYX4fQd4q9kyfW7HXwCJF/+JVUqWh+JqssRonv+9cw jSKg== X-Gm-Message-State: ACrzQf2MAMSIa/NnV81g6dqq/lmsUMGM58mxesDvg5oqYcvKMERQHXCq kUfKgm3m+pH2m+KuFX1RUxrVuw== X-Google-Smtp-Source: AMsMyM6bJdMa7N5QxnACd3Ttb0ThzapeCiUxb/MbTJVAXotHLUcV2tMCdTodRYT9wH43R9ASc1A4qg== X-Received: by 2002:a17:90b:1e49:b0:20b:36a3:aba6 with SMTP id pi9-20020a17090b1e4900b0020b36a3aba6mr6128720pjb.2.1666813357227; Wed, 26 Oct 2022 12:42:37 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:c9e3:74f3:6b2b:135]) by smtp.gmail.com with UTF8SMTPSA id s27-20020aa78bdb000000b0056bc30e618dsm3341776pfd.38.2022.10.26.12.42.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 12:42:36 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Guo , linux-mmc@vger.kernel.org, Adrian Hunter , Shawn Lin , Michal Simek , Sascha Hauer , Bjorn Andersson , Thierry Reding , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Jonathan Hunter , Andy Gross , Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Konrad Dybcio , Al Cooper , Fabio Estevam , Florian Fainelli , NXP Linux Team , Haibo Chen , Sowjanya Komatineni , Brian Norris Subject: [PATCH v4 4/7] mms: sdhci-esdhc-imx: Fix SDHCI_RESET_ALL for CQHCI Date: Wed, 26 Oct 2022 12:42:06 -0700 Message-Id: <20221026124150.v4.4.I7d01f9ad11bacdc9213dee61b7918982aea39115@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221026194209.3758834-1-briannorris@chromium.org> References: <20221026194209.3758834-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. This patch depends on (and should not compile without) the patch entitled "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Fixes: bb6e358169bf ("mmc: sdhci-esdhc-imx: add CMDQ support") Signed-off-by: Brian Norris Reviewed-by: Haibo Chen Acked-by: Adrian Hunter --- Changes in v4: - Add dependency notes - Add Adrian's Ack Changes in v3: - Use new SDHCI+CQHCI helper - Add Reviewed-by Changes in v2: - Drop unnecessary ESDHC_FLAG_CQHCI check drivers/mmc/host/sdhci-esdhc-imx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 55981b0f0b10..b297c3c360eb 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -25,6 +25,7 @@ #include #include #include +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "sdhci-esdhc.h" #include "cqhci.h" @@ -1288,7 +1289,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) static void esdhc_reset(struct sdhci_host *host, u8 mask) { - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);