From patchwork Fri Sep 30 11:29:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 611056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCC4CC43219 for ; Fri, 30 Sep 2022 11:39:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230510AbiI3LjD (ORCPT ); Fri, 30 Sep 2022 07:39:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231707AbiI3LiJ (ORCPT ); Fri, 30 Sep 2022 07:38:09 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A95D72645 for ; Fri, 30 Sep 2022 04:29:34 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id b24so4474593ljk.6 for ; Fri, 30 Sep 2022 04:29:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=kBJ/AhVm8NyzJ5+h26lm5F36R+jqwuRJqvXoFWsRPvg=; b=oB87pGB2PFzV5Gf3EtpMTgLZMT1tE9r0YwZHyLHPpbofeY2CmnGNk/U5Ohzyz8v6J9 nvT/GTxgj2h6YeI3G6ATt6yv8IKrzG1uEl4k2sCaMiPjrMpXnbOi+VfM37G0t7z6YK7N X4tfPuvM/VSdGZqEgBXSBPogSZuU+hco/523yqtyUZC18WJPcFoybnwmtDph3j9iurF1 sIyWxwoEMRZDpbjV/Qkf7T52HMRTGq0h8rn2uSlUT8qqH+QSF613SMd1WLsQ/lS/K1Tq AfR+YRqCDWz/CH0YsUSamfbG+2K6SoQHFluBfKvFCmJlCX+ZKFU4SeJkaipXLfUExaFX ug7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=kBJ/AhVm8NyzJ5+h26lm5F36R+jqwuRJqvXoFWsRPvg=; b=HhG95NLeME1k/gkqQ53pypqixzfIb8//iaAukGLovQeYpaP6kM03Jr4fsM/GxQoJUP FypkAjH8fCnUL8+9xx8+GE+cuqdP/iSQ6QnifOSEIrh0sYmrLJ7ertutHB4eYbDu6xsY cFQ6suS32wIfXzT9s2aIY2Aau6GlX8plymD67ZrIcz06E9c8Rdlwr0/YNA1qxHJ3yYQj txxeQCMP4qAubTTCgWh9zz72kDE86CDjXHttA94YCffySu0kltoDB/JMgs4hgn0AP58V 83vdeWD0//ib72iXnhXqkI1xH39o1ElNlZgd6At9rS9oZGAF4LPquMpVT6EOoZsULmvC FJOA== X-Gm-Message-State: ACrzQf2GiGHfk+GtQFPpSEInwMBeeE3B4E1u8HBM/nz9EFxFMGFYFFUc O31N+hlE91di/wNGeALdJuUxyA== X-Google-Smtp-Source: AMsMyM5gpu+E8tj81H4d5LKV7UvkbDlV8eZONF5PXgVawbYc9Y9hd0X0zi4JkkeWfHymsHYzwZ8kAA== X-Received: by 2002:a2e:a9a7:0:b0:26c:4ec7:fbf8 with SMTP id x39-20020a2ea9a7000000b0026c4ec7fbf8mr2614599ljq.413.1664537372512; Fri, 30 Sep 2022 04:29:32 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v18-20020a197412000000b0049493c14b17sm264672lfe.181.2022.09.30.04.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 04:29:32 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v2 06/12] phy: qcom-qmp-ufs: rename regs layout arrays Date: Fri, 30 Sep 2022 14:29:20 +0300 Message-Id: <20220930112926.638543-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930112926.638543-1-dmitry.baryshkov@linaro.org> References: <20220930112926.638543-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 4 +++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 31 ++++++++++--------- 2 files changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h index bcca23493b7e..43255e8bf038 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -8,6 +8,9 @@ #define QCOM_PHY_QMP_PCS_UFS_V5_H_ /* Only for QMP V5 PHY - UFS PCS registers */ +#define QPHY_V5_PCS_UFS_PHY_START 0x000 +#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V5_PCS_UFS_SW_RESET 0x008 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c @@ -21,6 +24,7 @@ #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 +#define QPHY_V5_PCS_UFS_READY_STATUS 0x180 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index c4d0bc9e6e83..064435c1b78d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -86,31 +86,32 @@ enum qphy_reg_layout { QPHY_LAYOUT_SIZE }; -static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, }; -static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, }; -static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, - [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, - [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, -}; - -static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; +static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, + [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), @@ -677,7 +678,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = msm8996_ufsphy_regs_layout, + .regs = ufsphy_v2_regs_layout, .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, @@ -701,7 +702,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sdm845_ufsphy_regs_layout, + .regs = ufsphy_v3_regs_layout, .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, @@ -725,7 +726,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm6115_ufsphy_regs_layout, + .regs = ufsphy_v2_regs_layout, .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, @@ -748,7 +749,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v4_regs_layout, .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, @@ -770,7 +771,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v5_regs_layout, .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, @@ -792,7 +793,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v5_regs_layout, .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN,