From patchwork Wed Sep 28 14:59:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 610200 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5A54C54EE9 for ; Wed, 28 Sep 2022 15:00:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234631AbiI1PAe (ORCPT ); Wed, 28 Sep 2022 11:00:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234611AbiI1PAL (ORCPT ); Wed, 28 Sep 2022 11:00:11 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E8A83207B for ; Wed, 28 Sep 2022 08:00:05 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id a14so14624370ljj.8 for ; Wed, 28 Sep 2022 08:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=rvkYwwXNz2RtbX8bEFgVafW/TqrLIdtASWYdL878aho=; b=OuC/T5e+XXTBa97Pq6H+Qtlxnn5uEKP9bv8POHCv4c8o8E41lXQEZYrMEG+br/Xt/5 jot9olxvi4OM9JaRVlRSzPiSBEi0RT2IHV9iGGlZGA8bSxqyM31ON+lPiFBch2e//U5R GunGB6g6XFDrM2pA/0wd3RBmkh4ltI/Odr1wZXwW8U6PDut7t36frzBniYTRv3HChRAA WmwRohD1jMIiuGWVpxwKMnStkw4X4sRTgd5kh0RHoGrEFAc8PBQJdiW+SymVaNFp5Wa7 c9nGUcfpZYKxOgw8fUW3UoRdInVA602NCRV+Jqv2oKwjLpxLqTWrJaOcNBNfktbeocVK 73jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=rvkYwwXNz2RtbX8bEFgVafW/TqrLIdtASWYdL878aho=; b=JvXZWz4a3NFnw9BqXLvjMzZXJw1adLuN4dvQKcvbJGuKKvAXKafjp5GDsXXCk5xJWr qFmwfWOrpgMzqhhAkjhVYYlZqeLdbkVG09xyoLkaHAvfCnSqAYNoyCkgNQ4t+coPMsrQ UiHD1H0xf1WAvTe8teXTDdEmiM497Mst2/b7fkWzJ/DsIASHknr/Q/nik/Zp5hspEmGJ /C8mUQdW8OqVC3A7j5s7l6NTgGK1OreRsvOvKcAF2FfX7xINskip9IhhE7twPkCAe35V avxwckXHRV3tpFFlmwuwuJwdQvm3/Kg8yVyMtQAGAXXNXFR6YRV4hfMtZD2+LAvLGFCB TEWQ== X-Gm-Message-State: ACrzQf2+2sI0NLm8MIhKBtGy8rj/S1k8qNf0EazzJC7VmY50oNShM6hg tMM5IUR3tqSqtpUDDucAGtU3NQ== X-Google-Smtp-Source: AMsMyM6/4NNhkvMUVhUNP+gjiceRZ1wl8M3ZN8oDWDeHGxn/4wdDMcsGvZgukXDWZYcgaxxyhohW8Q== X-Received: by 2002:a2e:958f:0:b0:26c:fd2:80b4 with SMTP id w15-20020a2e958f000000b0026c0fd280b4mr11203358ljh.147.1664377202947; Wed, 28 Sep 2022 08:00:02 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:02 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 04/11] clk: qcom: gcc-msm8974: move clock parent tables down Date: Wed, 28 Sep 2022 17:59:51 +0300 Message-Id: <20220928145958.376288-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-msm8974.c | 98 +++++++++++++++++----------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index b847ce852ef8..77f3497265a0 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -32,28 +32,6 @@ enum { P_GPLL4, }; -static const struct parent_map gcc_xo_gpll0_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 } -}; - -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0_vote", -}; - -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL4, 5 } -}; - -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0_vote", - "gpll4_vote", -}; - static struct clk_pll gpll0 = { .l_reg = 0x0004, .m_reg = 0x0008, @@ -81,6 +59,55 @@ static struct clk_regmap gpll0_vote = { }, }; +static struct clk_pll gpll4 = { + .l_reg = 0x1dc4, + .m_reg = 0x1dc8, + .n_reg = 0x1dcc, + .config_reg = 0x1dd4, + .mode_reg = 0x1dc0, + .status_reg = 0x1ddc, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll4_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_vote", + .parent_names = (const char *[]){ "gpll4" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 } +}; + +static const char * const gcc_xo_gpll0[] = { + "xo", + "gpll0_vote", +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 5 } +}; + +static const char * const gcc_xo_gpll0_gpll4[] = { + "xo", + "gpll0_vote", + "gpll4_vote", +}; + static struct clk_rcg2 config_noc_clk_src = { .cmd_rcgr = 0x0150, .hid_width = 5, @@ -144,33 +171,6 @@ static struct clk_regmap gpll1_vote = { }, }; -static struct clk_pll gpll4 = { - .l_reg = 0x1dc4, - .m_reg = 0x1dc8, - .n_reg = 0x1dcc, - .config_reg = 0x1dd4, - .mode_reg = 0x1dc0, - .status_reg = 0x1ddc, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll4", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll4_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_vote", - .parent_names = (const char *[]){ "gpll4" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { F(125000000, P_GPLL0, 1, 5, 24), { }