From patchwork Thu Sep 15 13:37:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 606252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7723EC6FA8D for ; Thu, 15 Sep 2022 13:38:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229728AbiIONh7 (ORCPT ); Thu, 15 Sep 2022 09:37:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229774AbiIONh4 (ORCPT ); Thu, 15 Sep 2022 09:37:56 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F57467170 for ; Thu, 15 Sep 2022 06:37:54 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id a8so30353279lff.13 for ; Thu, 15 Sep 2022 06:37:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=/rfng3AhNVbCjffD+zYL4fZIFA+szevKgvgA9KHfqnw=; b=jN1kwkWHYLDBiqe4bwBEbqLHts1QMAEfvWDh2CTwqApWS6f3jpDWR4QNkqI2kaZu0p cX95IngFmqlbm8YkuXpzbW4T54r8l/PWz7vLdr3p6gWEdX2AKMowkwpXP8Ty+Cl/NH5Y v7AOb8jzGhx1AruXm/DgvzKpg5CedgGU3gWqMq4CZ2CmYnSMU5izwU3zCmRnqyjRcQK8 TH4TInA1B1/pml9Pq/yoQ+MY4PNCQ3RSqZyb6cFibIjVU3KdYXN/QkUKj5dqtRNyjbYU Kft5OyCaS9PICOcDC5aNcVjWYbBU1+pW/DECqaZOmIN9IRgynSE48Oglit8FXWhp7JD4 1ZOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=/rfng3AhNVbCjffD+zYL4fZIFA+szevKgvgA9KHfqnw=; b=ghTs8odhfNf/42RTrkQHz9Y59OxrOz+CYMiNN2eAXXckqgxSoLgcOaN3k/AqAjtvwo qvAKZ01eyJQEioSo07eGujmJyuJ73TfI6xRQrC6iCZaPTOXkd1SMH8TcaQPYFK7KgUTT +xLLWtdgybVGY50D7OO9P5yuA/DiX1eI7ggL+M+MUOh9lJpVFZmLIGrnJP3mnmp+Aswt 34d2FO5w6zTRiv28sHCNz6lXIgyQYaXGC2WVRwsteV5ifoJfZGVonDiP79gbp9up82CN jy8TMLQqjS3CCvcDMHyK0dH0sxZceDumEKB9s9W35tR6+2oX6d3whX7ZCN5no8p/br42 q+JQ== X-Gm-Message-State: ACrzQf3Oww4GEIRnpYmtHyA7j7r+pDBCzLJgElK7NktybopvfHpZdsBq aXSCiMk595HqkqF/5eQiRu2iTA== X-Google-Smtp-Source: AA6agR7DxSf/jltB/uufDYnEUj+NWa15KLKu6xbVAL7SlezLzpUp8QvUZWRH9lFxruK+6c12yXKcsQ== X-Received: by 2002:a05:6512:a89:b0:49d:b866:6330 with SMTP id m9-20020a0565120a8900b0049db8666330mr2278101lfu.346.1663249073895; Thu, 15 Sep 2022 06:37:53 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 2-20020a2e0902000000b0026ad753448fsm3142634ljj.85.2022.09.15.06.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 06:37:53 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v7 12/12] dt-bindings: display/msm: add support for the display on SM8250 Date: Thu, 15 Sep 2022 16:37:42 +0300 Message-Id: <20220915133742.115218-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220915133742.115218-1-dmitry.baryshkov@linaro.org> References: <20220915133742.115218-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM8250 platform. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/mdss-common.yaml | 4 +- .../bindings/display/msm/qcom,sm8250-dpu.yaml | 92 ++++++++++++++++ .../display/msm/qcom,sm8250-mdss.yaml | 103 ++++++++++++++++++ 3 files changed, 197 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index 2a476bd0215e..27d7242657b2 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -27,11 +27,11 @@ properties: clocks: minItems: 2 - maxItems: 3 + maxItems: 4 clock-names: minItems: 2 - maxItems: 3 + maxItems: 4 interrupts: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml new file mode 100644 index 000000000000..9ff8a265c85f --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 Display DPU + +maintainers: + - Dmitry Baryshkov + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8250-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display ahb clock + - description: Display hf axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible = "qcom,sm8250-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml new file mode 100644 index 000000000000..ec806535b804 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 Display MDSS + +maintainers: + - Dmitry Baryshkov + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SM8250 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm8250-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8250-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^dsi-phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sm8250-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; +...