From patchwork Wed Aug 31 18:58:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 601874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83FB9ECAAD3 for ; Wed, 31 Aug 2022 18:59:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229710AbiHaS7o (ORCPT ); Wed, 31 Aug 2022 14:59:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232647AbiHaS7g (ORCPT ); Wed, 31 Aug 2022 14:59:36 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FDADC0E7D for ; Wed, 31 Aug 2022 11:58:39 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id k22so15569933ljg.2 for ; Wed, 31 Aug 2022 11:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9D4WLFfe/01foePAxbv2UpOqyUHDT522ukkHqFhUDEw=; b=LFrkdPc6yZ170ziUXu9DS5T2AuJwd25pHctJrwc5ZMUT9tGH/8kUdve89bqvb8nG3h 2DVdabyRhtitD2bc5dUpsYaaTrXMT1CzA9xL/CNtq6CsJYxiGE/GK3mZ3HTuGBvmuAGF Ch5t6WUGpyxw6ww4XRNKlzW9VphNLYGS7bD1hlMpv7QNu8r2jkNz/HtOunA2PVSQdX82 GTosFN12krEcNRrViGm/QkssUBn4f8EZ6ity6AnabB2HWKJ2vyrmRh7Yp7uP4u8dj87H KXQpZiAyx4d9BZa2GrLgeR9WqsCPEwJInd+q3VtO5vP+pHOcFxDt5ejvaa4eWVedUTrp /JPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9D4WLFfe/01foePAxbv2UpOqyUHDT522ukkHqFhUDEw=; b=PweT79Fnd7zK2T/Xb5vkBeDteQUv38s44CbFASoqrx1K6S3lPo4VAOWDOxfKII+mGl liFxlJOCWqjyQVbyqnzQZgB+EbQzaciwAjCFSkY3Kc9KCAbO7Tb83HiU0ZBgz8c22LXT md/VFq9mWs48eq9JyHXiQeF5Fp1ZXxKpH43z/xKjW4Rb9QO7K0b9kZDXjwyUOVnlYLZZ Q81P7gCtWmAXwsSpCGvw4E0oCWGj81xayAg2KiSObwsQoeeksABuTdVWLExgpZw/EpxK RVZxyEgJOosVotCC7iUqnrImsWGFERQ/8hfZRreeH2inr5RsGwgZr3dis6+j2nTT0GiS mg1Q== X-Gm-Message-State: ACgBeo0Yy5dye8vx05aLei1dcTS3cUAG6dqRw+wulPNYUM/fsu1KcziT vpuXaOab5ggQBkiWtoWdW+E8TQ== X-Google-Smtp-Source: AA6agR4nJjCWPAiS+IzhKTA9UtJipaKerBlU+7r6SQkpy5DLgWqL52aEvfgYWUIjAetjc1SosEXBsw== X-Received: by 2002:a2e:b5d3:0:b0:267:4da0:ce3b with SMTP id g19-20020a2eb5d3000000b002674da0ce3bmr2633475ljn.420.1661972317670; Wed, 31 Aug 2022 11:58:37 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g1-20020a0565123b8100b004948f583e6bsm322422lfv.138.2022.08.31.11.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 11:58:36 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno , Loic Poulain Subject: [PATCH v5 07/12] dt-bindings: display/msm: split dpu-sc7280 into DPU and MDSS parts Date: Wed, 31 Aug 2022 21:58:25 +0300 Message-Id: <20220831185830.1798676-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220831185830.1798676-1-dmitry.baryshkov@linaro.org> References: <20220831185830.1798676-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In order to make the schema more readable, split dpu-sc7280 into the DPU and MDSS parts, each one describing just a single device binding. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sc7280.yaml | 194 ++++++------------ .../bindings/display/msm/mdss-sc7280.yaml | 86 ++++++++ 2 files changed, 151 insertions(+), 129 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/mdss-sc7280.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml index 7dc624a26e2e..ba15f1ade556 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -9,79 +9,42 @@ title: Qualcomm Display DPU dt properties for SC7280 maintainers: - Krishna Manikandan -description: | - Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SC7280. +description: Device tree bindings for the SC7280 DPU display controller. allOf: - - $ref: /schemas/display/msm/mdss-common.yaml# + - $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sc7280-mdss + const: qcom,sc7280-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AHB clock from dispcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock - description: Display core clock + - description: Display vsync clock clock-names: items: + - const: bus + - const: nrt_bus - const: iface - - const: ahb + - const: lut - const: core - - iommus: - maxItems: 1 - - interconnects: - maxItems: 1 - - interconnect-names: - maxItems: 1 - -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. - unevaluatedProperties: false - - allOf: - - $ref: /schemas/display/msm/dpu-common.yaml# - - properties: - compatible: - const: qcom,sc7280-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync + - const: vsync unevaluatedProperties: false @@ -89,77 +52,50 @@ examples: - | #include #include - #include - #include #include - display-subsystem@ae00000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,sc7280-mdss"; - reg = <0xae00000 0x1000>; - reg-names = "mdss"; - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", - "ahb", - "core"; - - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; - interconnect-names = "mdp0-mem"; - - iommus = <&apps_smmu 0x900 0x402>; - ranges; - - display-controller@ae01000 { - compatible = "qcom,sc7280-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - power-domains = <&rpmhpd SC7280_CX>; - operating-points-v2 = <&mdp_opp_table>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf5_out: endpoint { - remote-endpoint = <&edp_in>; - }; - }; - }; - }; + display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; + }; }; ... diff --git a/Documentation/devicetree/bindings/display/msm/mdss-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/mdss-sc7280.yaml new file mode 100644 index 000000000000..db843412abf9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdss-sc7280.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/mdss-sc7280.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display MDSS dt properties for SC7280 + +maintainers: + - Krishna Manikandan + +description: | + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SC7280. + +allOf: + - $ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sc7280-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 1 + + interconnect-names: + maxItems: 1 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sc7280-dpu + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sc7280-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x900 0x402>; + ranges; + }; +...