From patchwork Thu Aug 18 20:18:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 598577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F8FDC32773 for ; Thu, 18 Aug 2022 20:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345463AbiHRUTe (ORCPT ); Thu, 18 Aug 2022 16:19:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345552AbiHRUT2 (ORCPT ); Thu, 18 Aug 2022 16:19:28 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69073BA178; Thu, 18 Aug 2022 13:19:27 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHqDXN016532; Thu, 18 Aug 2022 20:19:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=49/ZdAZUxCiKDfjQcXTCZ4ROswvz6J0Xt+JfcKA4umk=; b=CO3VSa9rtdE2QCtCDW0mv5sgqal+mZYUppLSUvVuvuZmSzkt5pQfXjh9JE4pwQbrEYHd tNLee6vMI9O6vZMRxh4IPSzr3+41ASV7HHfkTuaZHroRuCoZ2HFNS7A7O3TtljCJhRNm Ks2cqKAHrlpQnALXTG9D/K4N1JZayZY/7gyMkwfIG3wNNXGK8u4Wa6Bc2m82E5ykFtid yHAnqUy61h8TcxttjN1SXTdZ7gHaffUqdgYhTWYnHSTS2Mqgf/xvhegh/7N7fBkEUuE3 gJ7JbSUocuA/FJGLoYA87BNfRgcBzzUsG0056S+ruZvTzLiG8AQpi/ByUQUEQPB2Rvkg Og== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3j12hhnsh6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 20:19:20 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27IKJIku019915 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 20:19:18 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 18 Aug 2022 13:19:14 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" , Dmitry Baryshkov CC: Douglas Anderson , , Akhil P Oommen , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , , Subject: [PATCH v3 4/5] clk: qcom: gpucc-sc7280: Add cx collapse reset support Date: Fri, 19 Aug 2022 01:48:38 +0530 Message-ID: <20220819014758.v3.4.I5e64ff4b77bb9079eb2edeea8a02585c9e76778f@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1660853919-987-1-git-send-email-quic_akhilpo@quicinc.com> References: <1660853919-987-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: QcR8wZvnG8nVExwilUhiBgMChlWwFb9H X-Proofpoint-ORIG-GUID: QcR8wZvnG8nVExwilUhiBgMChlWwFb9H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_14,2022-08-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208180074 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Allow a consumer driver to poll for cx gdsc collapse through Reset framework. Signed-off-by: Akhil P Oommen --- Changes in v3: - Convert 'struct qcom_reset_ops cx_gdsc_reset' to 'static const' (Krzysztof) Changes in v2: - Minor update to use the updated custom reset ops implementation drivers/clk/qcom/gpucc-sc7280.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 9a832f2..fece3f4 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -433,12 +433,22 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = { .fast_io = true, }; +static const struct qcom_reset_ops cx_gdsc_reset = { + .reset = gdsc_wait_for_collapse, +}; + +static const struct qcom_reset_map gpucc_sc7280_resets[] = { + [GPU_CX_COLLAPSE] = { .ops = &cx_gdsc_reset, .priv = &cx_gdsc }, +}; + static const struct qcom_cc_desc gpu_cc_sc7280_desc = { .config = &gpu_cc_sc7280_regmap_config, .clks = gpu_cc_sc7280_clocks, .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks), .gdscs = gpu_cc_sc7180_gdscs, .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs), + .resets = gpucc_sc7280_resets, + .num_resets = ARRAY_SIZE(gpucc_sc7280_resets), }; static const struct of_device_id gpu_cc_sc7280_match_table[] = {