From patchwork Sat Jul 30 09:40:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 594536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15731C04A68 for ; Sat, 30 Jul 2022 09:42:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235802AbiG3JmG (ORCPT ); Sat, 30 Jul 2022 05:42:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235940AbiG3Jll (ORCPT ); Sat, 30 Jul 2022 05:41:41 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54CD342AE8; Sat, 30 Jul 2022 02:41:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1659174099; x=1690710099; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=kapmk1TSxsuqJu2Jmg3cD+1eM1kpd48XieGg2BZn+oA=; b=vRWo+bktKG2J42YLJl4WF8wqZvH0nPXlBymPXvoi1/lZ3S1xWsPxHCD3 vdveVDxuoEW6CbZU//YObsacDB3INNQxuEf4QmTdi+fu1YQrtp0NUIZ83 cCKOyAXfy8mZg2pBfmNlvEGSJ2pFBV5/QF0j5NQVH7+nM6T9gJecPb1as s=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 30 Jul 2022 02:41:39 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2022 02:41:38 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:41:37 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:41:32 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson CC: Jordan Crouse , Jonathan Marek , Douglas Anderson , "Matthias Kaehlcke" , Akhil P Oommen , Abhinav Kumar , Chia-I Wu , Daniel Vetter , David Airlie , "Dmitry Baryshkov" , Philipp Zabel , Sean Paul , Stephen Boyd , Subject: [PATCH v3 5/8] drm/msm/a6xx: Ensure CX collapse during gpu recovery Date: Sat, 30 Jul 2022 15:10:48 +0530 Message-ID: <20220730150952.v3.5.I176567525af2b9439a7e485d0ca130528666a55c@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1659174051-27816-1-git-send-email-quic_akhilpo@quicinc.com> References: <1659174051-27816-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Because there could be transient votes from other drivers/tz/hyp which may keep the cx gdsc enabled, we should poll until cx gdsc collapses. We can use the reset framework to poll for cx gdsc collapse from gpucc clk driver. This feature requires support from the platform's gpucc driver. Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- Changes in v3: - Use reset interface from gpucc driver to poll for cx gdsc collapse https://patchwork.freedesktop.org/series/106860/ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++++ drivers/gpu/drm/msm/msm_gpu.c | 4 ++++ drivers/gpu/drm/msm/msm_gpu.h | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 1b049c5..721d5e6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,6 +10,7 @@ #include #include +#include #include #define GPU_PAS_ID 13 @@ -1224,6 +1225,9 @@ static void a6xx_recover(struct msm_gpu *gpu) /* And the final one from recover worker */ pm_runtime_put_sync(&gpu->pdev->dev); + /* Call into gpucc driver to poll for cx gdsc collapse */ + reset_control_reset(gpu->cx_collapse); + pm_runtime_use_autosuspend(&gpu->pdev->dev); if (active_submits) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 07e55a6..4a57627 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include /* @@ -903,6 +904,9 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, if (IS_ERR(gpu->gpu_cx)) gpu->gpu_cx = NULL; + gpu->cx_collapse = devm_reset_control_get_optional(&pdev->dev, + "cx_collapse"); + gpu->pdev = pdev; platform_set_drvdata(pdev, &gpu->adreno_smmu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 6def008..ab59fd2 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -13,6 +13,7 @@ #include #include #include +#include #include "msm_drv.h" #include "msm_fence.h" @@ -268,6 +269,9 @@ struct msm_gpu { bool hw_apriv; struct thermal_cooling_device *cooling; + + /* To poll for cx gdsc collapse during gpu recovery */ + struct reset_control *cx_collapse; }; static inline struct msm_gpu *dev_to_gpu(struct device *dev)