| Message ID | 20220726203401.595934-2-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v1,1/4] phy: qcom-qmp-pcie: split register tables into primary and secondary part | expand |
On Tue, Jul 26, 2022 at 11:33:58PM +0300, Dmitry Baryshkov wrote: > Split register tables list into primary and secondary parts. It is good to provide some reasoning on why splitting the register tables is required. > While we > are at it, drop unused if (table) conditions, since the function > qcom_qmp_phy_pcie_configure_lane() has this check anyway. > Please add a separate patch for the "while at it..." portion since that's a separate issue and the patch should come before this patch. > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 156 +++++++++++++---------- > 1 file changed, 87 insertions(+), 69 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > index 2d65e1f56bfc..e6272bd3d735 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > @@ -1346,34 +1346,33 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { > > struct qmp_phy; > > -/* struct qmp_phy_cfg - per-PHY initialization config */ > -struct qmp_phy_cfg { > - /* phy-type - PCIE/UFS/USB */ > - unsigned int type; > - /* number of lanes provided by phy */ > - int nlanes; > - > - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ > +struct qmp_phy_cfg_tables { > const struct qmp_phy_init_tbl *serdes_tbl; > int serdes_tbl_num; > - const struct qmp_phy_init_tbl *serdes_tbl_sec; > - int serdes_tbl_num_sec; > const struct qmp_phy_init_tbl *tx_tbl; > int tx_tbl_num; > - const struct qmp_phy_init_tbl *tx_tbl_sec; > - int tx_tbl_num_sec; > const struct qmp_phy_init_tbl *rx_tbl; > int rx_tbl_num; > - const struct qmp_phy_init_tbl *rx_tbl_sec; > - int rx_tbl_num_sec; > const struct qmp_phy_init_tbl *pcs_tbl; > int pcs_tbl_num; > - const struct qmp_phy_init_tbl *pcs_tbl_sec; > - int pcs_tbl_num_sec; > const struct qmp_phy_init_tbl *pcs_misc_tbl; > int pcs_misc_tbl_num; > - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; > - int pcs_misc_tbl_num_sec; > +}; > + > +/* struct qmp_phy_cfg - per-PHY initialization config */ > +struct qmp_phy_cfg { > + /* phy-type - PCIE/UFS/USB */ > + unsigned int type; > + /* number of lanes provided by phy */ > + int nlanes; > + > + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ > + struct qmp_phy_cfg_tables primary; > + /* > + * Init sequence for PHY blocks, providing additional register > + * programming. Unless required it can be left omitted. > + */ > + struct qmp_phy_cfg_tables secondary; > > /* clock ids to be requested */ > const char * const *clk_list; > @@ -1396,7 +1395,7 @@ struct qmp_phy_cfg { > > /* true, if PHY needs delay after POWER_DOWN */ > bool has_pwrdn_delay; > - /* power_down delay in usec */ > + /* power_down delay in usecondary */ usec is micro seconds, isn't it? Rest look good. Thanks, Mani > int pwrdn_delay_min; > int pwrdn_delay_max; > > @@ -1517,6 +1516,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 1, > > + .primary = { > .serdes_tbl = ipq8074_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), > .tx_tbl = ipq8074_pcie_tx_tbl, > @@ -1525,6 +1525,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { > .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), > .pcs_tbl = ipq8074_pcie_pcs_tbl, > .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), > + }, > .clk_list = ipq8074_pciephy_clk_l, > .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), > .reset_list = ipq8074_pciephy_reset_l, > @@ -1546,6 +1547,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 1, > > + .primary = { > .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), > .tx_tbl = ipq8074_pcie_gen3_tx_tbl, > @@ -1554,6 +1556,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { > .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), > .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, > .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), > + }, > .clk_list = ipq8074_pciephy_clk_l, > .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), > .reset_list = ipq8074_pciephy_reset_l, > @@ -1576,6 +1579,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 1, > > + .primary = { > .serdes_tbl = ipq6018_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), > .tx_tbl = ipq6018_pcie_tx_tbl, > @@ -1586,6 +1590,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { > .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), > .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl, > .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), > + }, > .clk_list = ipq8074_pciephy_clk_l, > .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), > .reset_list = ipq8074_pciephy_reset_l, > @@ -1606,6 +1611,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 1, > > + .primary = { > .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), > .tx_tbl = sdm845_qmp_pcie_tx_tbl, > @@ -1616,6 +1622,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { > .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), > .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, > .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), > + }, > .clk_list = sdm845_pciephy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), > .reset_list = sdm845_pciephy_reset_l, > @@ -1637,6 +1644,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 1, > > + .primary = { > .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), > .tx_tbl = sdm845_qhp_pcie_tx_tbl, > @@ -1645,6 +1653,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { > .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), > .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, > .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), > + }, > .clk_list = sdm845_pciephy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), > .reset_list = sdm845_pciephy_reset_l, > @@ -1666,24 +1675,28 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 1, > > + .primary = { > .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), > - .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, > - .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), > .tx_tbl = sm8250_qmp_pcie_tx_tbl, > .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), > .rx_tbl = sm8250_qmp_pcie_rx_tbl, > .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), > - .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, > - .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), > .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, > .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), > - .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, > - .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), > .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, > .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), > - .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, > - .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), > + }, > + .secondary = { > + .serdes_tbl = sm8250_qmp_gen3x1_pcie_serdes_tbl, > + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), > + .rx_tbl = sm8250_qmp_gen3x1_pcie_rx_tbl, > + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), > + .pcs_tbl = sm8250_qmp_gen3x1_pcie_pcs_tbl, > + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), > + .pcs_misc_tbl = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, > + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), > + }, > .clk_list = sdm845_pciephy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), > .reset_list = sdm845_pciephy_reset_l, > @@ -1705,24 +1718,28 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 2, > > + .primary = { > .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), > .tx_tbl = sm8250_qmp_pcie_tx_tbl, > .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), > - .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, > - .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), > .rx_tbl = sm8250_qmp_pcie_rx_tbl, > .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), > - .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, > - .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), > .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, > .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), > - .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, > - .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), > .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, > .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), > - .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, > - .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), > + }, > + .secondary = { > + .tx_tbl = sm8250_qmp_gen3x2_pcie_tx_tbl, > + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), > + .rx_tbl = sm8250_qmp_gen3x2_pcie_rx_tbl, > + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), > + .pcs_tbl = sm8250_qmp_gen3x2_pcie_pcs_tbl, > + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), > + .pcs_misc_tbl = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, > + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), > + }, > .clk_list = sdm845_pciephy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), > .reset_list = sdm845_pciephy_reset_l, > @@ -1745,6 +1762,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 1, > > + .primary = { > .serdes_tbl = msm8998_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), > .tx_tbl = msm8998_pcie_tx_tbl, > @@ -1753,6 +1771,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { > .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), > .pcs_tbl = msm8998_pcie_pcs_tbl, > .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), > + }, > .clk_list = msm8996_phy_clk_l, > .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), > .reset_list = ipq8074_pciephy_reset_l, > @@ -1770,6 +1789,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 1, > > + .primary = { > .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), > .tx_tbl = sc8180x_qmp_pcie_tx_tbl, > @@ -1780,6 +1800,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { > .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), > .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, > .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), > + }, > .clk_list = sdm845_pciephy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), > .reset_list = sdm845_pciephy_reset_l, > @@ -1800,6 +1821,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 2, > > + .primary = { > .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), > .tx_tbl = sdx55_qmp_pcie_tx_tbl, > @@ -1810,6 +1832,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { > .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), > .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, > .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), > + }, > .clk_list = sdm845_pciephy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), > .reset_list = sdm845_pciephy_reset_l, > @@ -1832,6 +1855,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 1, > > + .primary = { > .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), > .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, > @@ -1842,6 +1866,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { > .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), > .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, > .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), > + }, > .clk_list = sdm845_pciephy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), > .reset_list = sdm845_pciephy_reset_l, > @@ -1863,6 +1888,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { > .type = PHY_TYPE_PCIE, > .nlanes = 2, > > + .primary = { > .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, > .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), > .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, > @@ -1873,6 +1899,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { > .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), > .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, > .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), > + }, > .clk_list = sdm845_pciephy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), > .reset_list = sdm845_pciephy_reset_l, > @@ -1926,13 +1953,9 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) > { > const struct qmp_phy_cfg *cfg = qphy->cfg; > void __iomem *serdes = qphy->serdes; > - const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; > - int serdes_tbl_num = cfg->serdes_tbl_num; > > - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); > - if (cfg->serdes_tbl_sec) > - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, > - cfg->serdes_tbl_num_sec); > + qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->primary.serdes_tbl, cfg->primary.serdes_tbl_num); > + qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->secondary.serdes_tbl, cfg->secondary.serdes_tbl_num); > > return 0; > } > @@ -2036,46 +2059,41 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) > > /* Tx, Rx, and PCS configurations */ > qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, > - cfg->tx_tbl, cfg->tx_tbl_num, 1); > - if (cfg->tx_tbl_sec) > - qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, > - cfg->tx_tbl_num_sec, 1); > + cfg->primary.tx_tbl, cfg->primary.tx_tbl_num, 1); > + qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, > + cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 1); > > /* Configuration for other LANE for USB-DP combo PHY */ > if (cfg->is_dual_lane_phy) { > qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, > - cfg->tx_tbl, cfg->tx_tbl_num, 2); > - if (cfg->tx_tbl_sec) > - qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, > - cfg->tx_tbl_sec, > - cfg->tx_tbl_num_sec, 2); > + cfg->primary.tx_tbl, cfg->primary.tx_tbl_num, 2); > + qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, > + cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 2); > } > > qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, > - cfg->rx_tbl, cfg->rx_tbl_num, 1); > - if (cfg->rx_tbl_sec) > - qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, > - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); > + cfg->primary.rx_tbl, cfg->primary.rx_tbl_num, 1); > + qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, > + cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 1); > > if (cfg->is_dual_lane_phy) { > qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, > - cfg->rx_tbl, cfg->rx_tbl_num, 2); > - if (cfg->rx_tbl_sec) > - qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, > - cfg->rx_tbl_sec, > - cfg->rx_tbl_num_sec, 2); > + cfg->primary.rx_tbl, cfg->primary.rx_tbl_num, 2); > + qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, > + cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 2); > } > > - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); > - if (cfg->pcs_tbl_sec) > - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, > - cfg->pcs_tbl_num_sec); > - > - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, > - cfg->pcs_misc_tbl_num); > - if (cfg->pcs_misc_tbl_sec) > - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, > - cfg->pcs_misc_tbl_num_sec); > + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, > + cfg->primary.pcs_tbl, cfg->primary.pcs_tbl_num); > + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, > + cfg->secondary.pcs_tbl, cfg->secondary.pcs_tbl_num); > + > + qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, > + cfg->primary.pcs_misc_tbl, > + cfg->primary.pcs_misc_tbl_num); > + qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, > + cfg->secondary.pcs_misc_tbl, > + cfg->secondary.pcs_misc_tbl_num); > > /* > * Pull out PHY from POWER DOWN state. > -- > 2.35.1 >
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2d65e1f56bfc..e6272bd3d735 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1346,34 +1346,33 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { struct qmp_phy; -/* struct qmp_phy_cfg - per-PHY initialization config */ -struct qmp_phy_cfg { - /* phy-type - PCIE/UFS/USB */ - unsigned int type; - /* number of lanes provided by phy */ - int nlanes; - - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ +struct qmp_phy_cfg_tables { const struct qmp_phy_init_tbl *serdes_tbl; int serdes_tbl_num; - const struct qmp_phy_init_tbl *serdes_tbl_sec; - int serdes_tbl_num_sec; const struct qmp_phy_init_tbl *tx_tbl; int tx_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl_sec; - int tx_tbl_num_sec; const struct qmp_phy_init_tbl *rx_tbl; int rx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl_sec; - int rx_tbl_num_sec; const struct qmp_phy_init_tbl *pcs_tbl; int pcs_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl_sec; - int pcs_tbl_num_sec; const struct qmp_phy_init_tbl *pcs_misc_tbl; int pcs_misc_tbl_num; - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; - int pcs_misc_tbl_num_sec; +}; + +/* struct qmp_phy_cfg - per-PHY initialization config */ +struct qmp_phy_cfg { + /* phy-type - PCIE/UFS/USB */ + unsigned int type; + /* number of lanes provided by phy */ + int nlanes; + + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + struct qmp_phy_cfg_tables primary; + /* + * Init sequence for PHY blocks, providing additional register + * programming. Unless required it can be left omitted. + */ + struct qmp_phy_cfg_tables secondary; /* clock ids to be requested */ const char * const *clk_list; @@ -1396,7 +1395,7 @@ struct qmp_phy_cfg { /* true, if PHY needs delay after POWER_DOWN */ bool has_pwrdn_delay; - /* power_down delay in usec */ + /* power_down delay in usecondary */ int pwrdn_delay_min; int pwrdn_delay_max; @@ -1517,6 +1516,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, + .primary = { .serdes_tbl = ipq8074_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), .tx_tbl = ipq8074_pcie_tx_tbl, @@ -1525,6 +1525,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), .pcs_tbl = ipq8074_pcie_pcs_tbl, .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), + }, .clk_list = ipq8074_pciephy_clk_l, .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), .reset_list = ipq8074_pciephy_reset_l, @@ -1546,6 +1547,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, + .primary = { .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), .tx_tbl = ipq8074_pcie_gen3_tx_tbl, @@ -1554,6 +1556,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), + }, .clk_list = ipq8074_pciephy_clk_l, .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), .reset_list = ipq8074_pciephy_reset_l, @@ -1576,6 +1579,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, + .primary = { .serdes_tbl = ipq6018_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), .tx_tbl = ipq6018_pcie_tx_tbl, @@ -1586,6 +1590,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl, .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), + }, .clk_list = ipq8074_pciephy_clk_l, .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), .reset_list = ipq8074_pciephy_reset_l, @@ -1606,6 +1611,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, + .primary = { .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), .tx_tbl = sdm845_qmp_pcie_tx_tbl, @@ -1616,6 +1622,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), + }, .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, @@ -1637,6 +1644,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, + .primary = { .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), .tx_tbl = sdm845_qhp_pcie_tx_tbl, @@ -1645,6 +1653,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), + }, .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, @@ -1666,24 +1675,28 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, + .primary = { .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), - .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, - .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), .tx_tbl = sm8250_qmp_pcie_tx_tbl, .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), .rx_tbl = sm8250_qmp_pcie_rx_tbl, .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), - .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, - .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), - .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, - .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), - .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), + }, + .secondary = { + .serdes_tbl = sm8250_qmp_gen3x1_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), + .rx_tbl = sm8250_qmp_gen3x1_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), + .pcs_tbl = sm8250_qmp_gen3x1_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc_tbl = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), + }, .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, @@ -1705,24 +1718,28 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 2, + .primary = { .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), .tx_tbl = sm8250_qmp_pcie_tx_tbl, .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), - .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, - .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), .rx_tbl = sm8250_qmp_pcie_rx_tbl, .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), - .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, - .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), - .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, - .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), - .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, - .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .secondary = { + .tx_tbl = sm8250_qmp_gen3x2_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), + .rx_tbl = sm8250_qmp_gen3x2_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), + .pcs_tbl = sm8250_qmp_gen3x2_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc_tbl = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), + }, .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, @@ -1745,6 +1762,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, + .primary = { .serdes_tbl = msm8998_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), .tx_tbl = msm8998_pcie_tx_tbl, @@ -1753,6 +1771,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), .pcs_tbl = msm8998_pcie_pcs_tbl, .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), + }, .clk_list = msm8996_phy_clk_l, .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), .reset_list = ipq8074_pciephy_reset_l, @@ -1770,6 +1789,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, + .primary = { .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), .tx_tbl = sc8180x_qmp_pcie_tx_tbl, @@ -1780,6 +1800,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), + }, .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, @@ -1800,6 +1821,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 2, + .primary = { .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), .tx_tbl = sdx55_qmp_pcie_tx_tbl, @@ -1810,6 +1832,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), + }, .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, @@ -1832,6 +1855,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 1, + .primary = { .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, @@ -1842,6 +1866,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), + }, .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, @@ -1863,6 +1888,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .type = PHY_TYPE_PCIE, .nlanes = 2, + .primary = { .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, @@ -1873,6 +1899,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), + }, .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, @@ -1926,13 +1953,9 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; - const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; - int serdes_tbl_num = cfg->serdes_tbl_num; - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); - if (cfg->serdes_tbl_sec) - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, - cfg->serdes_tbl_num_sec); + qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->primary.serdes_tbl, cfg->primary.serdes_tbl_num); + qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->secondary.serdes_tbl, cfg->secondary.serdes_tbl_num); return 0; } @@ -2036,46 +2059,41 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) /* Tx, Rx, and PCS configurations */ qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 1); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 1); + cfg->primary.tx_tbl, cfg->primary.tx_tbl_num, 1); + qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, + cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 1); /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 2); + cfg->primary.tx_tbl, cfg->primary.tx_tbl_num, 2); + qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, + cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 2); } qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); + cfg->primary.rx_tbl, cfg->primary.rx_tbl_num, 1); + qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, + cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 1); if (cfg->is_dual_lane_phy) { qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl_sec, - cfg->rx_tbl_num_sec, 2); + cfg->primary.rx_tbl, cfg->primary.rx_tbl_num, 2); + qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, + cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 2); } - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - if (cfg->pcs_tbl_sec) - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, - cfg->pcs_tbl_num_sec); - - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, - cfg->pcs_misc_tbl_num); - if (cfg->pcs_misc_tbl_sec) - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, - cfg->pcs_misc_tbl_num_sec); + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, + cfg->primary.pcs_tbl, cfg->primary.pcs_tbl_num); + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, + cfg->secondary.pcs_tbl, cfg->secondary.pcs_tbl_num); + + qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, + cfg->primary.pcs_misc_tbl, + cfg->primary.pcs_misc_tbl_num); + qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, + cfg->secondary.pcs_misc_tbl, + cfg->secondary.pcs_misc_tbl_num); /* * Pull out PHY from POWER DOWN state.
Split register tables list into primary and secondary parts. While we are at it, drop unused if (table) conditions, since the function qcom_qmp_phy_pcie_configure_lane() has this check anyway. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 156 +++++++++++++---------- 1 file changed, 87 insertions(+), 69 deletions(-)