From patchwork Wed Jul 13 13:13:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 590100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51B4CC433EF for ; Wed, 13 Jul 2022 13:18:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236276AbiGMNSD (ORCPT ); Wed, 13 Jul 2022 09:18:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236212AbiGMNSA (ORCPT ); Wed, 13 Jul 2022 09:18:00 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 825FA5F6B; Wed, 13 Jul 2022 06:17:59 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 13B8E61CC1; Wed, 13 Jul 2022 13:17:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A1DF0C341CA; Wed, 13 Jul 2022 13:17:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657718277; bh=vkbptp5oByb0OIdbEDrykCuoBKNZ8jnXeKx9uCOm2XA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oG5/bH/f1vecfU25hwe8kdKoNoAsi+g3mjXqhHGOkauOcGkv3RMRanZNMs1st9H07 8KOezumB6vRk6WH+/0iMy5rsIqDFuv3fAg97MXvB7+VnmcWMnjZi3ekjiAbILt5MDN u2Ewu2wxBSgu86xD+BTtk1aYpsD5sOGxT3V5OfKXTXdImeb/x6mnwl0tuDUnSl2Dwd EhnZLujLCO/hsbap104Sjo8yhMCBN72oV4nL/FpQwQbjXW3XRL4gncsZfyVvGFbUp3 D1YCJpZeG/mTup4IcrGbGiu4AFnbaD+WiV66zO9/bokkqAz7M51/z73s2t+3J9nvXw lumBQ/LlB3K2Q== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oBcFd-0007gV-KS; Wed, 13 Jul 2022 15:18:01 +0200 From: Johan Hovold To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Bjorn Andersson Cc: Andy Gross , Konrad Dybcio , Wesley Cheng , linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 7/7] arm64: dts: qcom: reorder USB interrupts Date: Wed, 13 Jul 2022 15:13:40 +0200 Message-Id: <20220713131340.29401-8-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220713131340.29401-1-johan+linaro@kernel.org> References: <20220713131340.29401-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Three SoCs did not follow the interrupt order specified by the USB controller binding. While keeping the non-SuperSpeed interrupts together seems natural, reorder the interrupts to match the binding. Signed-off-by: Johan Hovold Acked-by: Krzysztof Kozlowski --- arch/arm/boot/dts/qcom-sdx65.dtsi | 10 ++++++---- arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++++++++-------- arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++++-------- 3 files changed, 30 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 7a193678b4f5..8daefd50217a 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -372,11 +372,13 @@ usb: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 19 IRQ_TYPE_EDGE_BOTH>, <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 18 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "ss_phy_irq", "dm_hs_phy_irq"; + <&pdc 18 IRQ_TYPE_EDGE_BOTH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7ac8aa110f81..65be7f3ec74c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3026,11 +3026,13 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -3081,11 +3083,13 @@ usb_2: usb@a8f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 12 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 65c7fe54613d..e72a04411888 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2461,11 +2461,13 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -2509,11 +2511,13 @@ usb_2: usb@a8f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 12 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>;