From patchwork Tue Jul 5 09:42:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 587499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C4BFCCA47B for ; Tue, 5 Jul 2022 09:49:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232126AbiGEJtr (ORCPT ); Tue, 5 Jul 2022 05:49:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231721AbiGEJtV (ORCPT ); Tue, 5 Jul 2022 05:49:21 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7BE913D39; Tue, 5 Jul 2022 02:49:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id DAD41CE1AFA; Tue, 5 Jul 2022 09:49:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1EBD4C36B0E; Tue, 5 Jul 2022 09:49:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657014543; bh=rhNsOHQahugNBTZT3MMRtc7ithk9F73meRh37KBt6SU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tyQz+Wgym2AuX6jhwblsZldHtml7BDtJLxw2NcC+GDqXof0E1X5EBrvteaFpWZ921 jheWa3VyJ8cfhSlx8fSXG2TcnJSlzRZJQDJx2NXTzexUmwsXkASJBGwh1GdR9Gss8+ OkMBuaAPA0Z9vAtI9Ivp6hFCXgKp1w3gfB8BCxmisjM1M2L9mDoS7ci8tD/DEKHyN+ RfT7gJTZb0wPTJ6rtPO2Ky5PXJ6WDLfGSwEsbH7yU2SjA3m6Zgo79Ax1wgbtDxvpdq pA56yVKZ8aJ2YZ5FNrpP0R03YgIlphTDAcbJuXbnVYLYqIg7xhKSdk+HQi1qzc+QjV O/XUzoEt3G40A== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1o8fB2-0004Xg-4g; Tue, 05 Jul 2022 11:49:04 +0200 From: Johan Hovold To: Vinod Koul , Rob Herring , Krzysztof Kozlowski Cc: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 18/43] dt-bindings: phy: qcom,qmp-pcie: add example node Date: Tue, 5 Jul 2022 11:42:14 +0200 Message-Id: <20220705094239.17174-19-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220705094239.17174-1-johan+linaro@kernel.org> References: <20220705094239.17174-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add an example node based on a cleaned up version of sm8250.dtsi. Signed-off-by: Johan Hovold --- .../bindings/phy/qcom,qmp-pcie-phy.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml index 5a1ebf874559..3fc08af41144 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml @@ -262,3 +262,44 @@ allOf: properties: reg: minItems: 4 + +examples: + - | + #include + phy-wrapper@1c0e000 { + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; + reg = <0x01c0e000 0x1c0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x01c0e000 0x1000>; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + phy@200 { + reg = <0x200 0x170>, + <0x400 0x200>, + <0xa00 0x1f0>, + <0x600 0x170>, + <0x800 0x200>, + <0xe00 0xf4>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + }; + };